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Lukas K edited this page Sep 17, 2016 · 8 revisions

RISC-V

This document provides the most important information about RISC V. The full specification of RISC V can be found here: http://riscv.org/specifications/

Important RISC-V Instructions

The following instructions exist within RISC-V and should be implemented in the architecture interpreter.

RV32I Base Integer Instruction Set

These instructions are the base of all RISC-V processors.

OP-IMM

Integer Register-Immediate Instructions. In general 12 bit immediates are used.

  • ADDI dest, src, imm ; Sign extended, ignores arithmetic overflow, stores the lower 32 bits of the result in dest
  • SLTI dest, src, imm ; Set less than immediate.
  • SLTIU dest, src, imm ; Set less than immediate unsigned.
  • ANDI dest, src, imm
  • ORI dest, src, imm
  • XORI dest, src, imm
  • SLLI dest, src, imm ; Logical left shift with 5 bit imm
  • SRLI dest, src, imm ; Logical right shift with 5 bit imm
  • SRAI dest, src, imm ; Arithmetical right shift with 5 bit imm

LUI

Load upper immediate.

  • LUI dest, imm ; Stores the 20 bit immediate in the upper bits of dest (Can be used to build integer constants: First the upper bits are loaded, and then the lower bits are ORed via the ORI instruction).

AUIPC

Add upper immediate to pc.

  • AUIPC dest, imm ; Adds the 20 bit immediate to the upper bits of the pc and stores the result in dest (Can be used to jump anywere in combination with the JALR instruction).

OP

Integer Register-Register Operations.

  • ADD dest, src1, src2
  • SLT dest, src1, src2 ; dest = 1 if src1 < src2, dest = 0 otherwise
  • SLTU dest, src1, src2 ; like above but unsigned
  • AND dest, src1, src2
  • OR dest, src1, src2
  • XOR dest, src, src2
  • SLL dest, src1, src2 ; Shift left src1 with lower 5 bits of src2
  • SRL dest, src1, src2 ; like above respectively
  • SUB dest, src1, src2
  • SRA dest, src1, src2 ; Arithmetical shift respectively

JAL

Jump And link (or unconditional jumps).

  • JAL dest, offset ; Offset is 20 bit (signed) and interpreted as a multiples of 2 bytes. So offset*2 is added to the pc. The address of the instruction following after the jump is stored in dest.

JALR

Jump and link register (or unconditional jumps).

  • JALR dest, base, offset ; The pc is set to base + offset (12 bit) with setting the least significant bit to 0. The adress of the instruction following after the jump is stored in dest.

BRANCH

Branch instructions compare two registers (or conditional jumps). They use a 12 bit offset, multiplied by 2. If the condition succeeds, the offset will be added to the pc to give the target address.

  • BEQ src1, src2, offset ; src1 == src2
  • BNE src1, src2, offset ; src1 != src2
  • BLT src1, src2, offset ; signed rs1 < rs2
  • BLTU src1, src2, offset ; unsigned rs1 < rs2
  • BGE src1, src2, offset ; signed rs1 >= rs2
  • BGEU src1, src2, offset ; unsigned rs1 >= rs2

Additionally, BGT, BGTU, BLE and BLEU can be constructed using the instructions above.

LOAD

Loads copy from memory in register. The address is obtained by adding base + offset (12 bit).

  • LW dest, base, offset ; 32 bit
  • LH dest, base, offset ; sign extends 16 bits
  • LHU dest, base, offset ; zero extends 16 bits
  • LB dest, base, offset ; sign extends 8 bits
  • LBU dest, base, offset ; zero extends 8 bits

STORE

Stores copy from register and write into memory. The address is obtained by adding base + offset (12 bit).

  • SW base, src, offset ; 32 bits
  • SH base, src, offset ; lower 16 bits of src
  • SB base, src, offset ; lower 8 bits of src

"M" Extension for for Integer Multiplication and Division

Only the instructions for RV32 are listed.

Multiplication

  • MUL dest, src1, src2 ; Places lower 32 bits of multiplication in dest
  • MULH dest, src, src2 ; Places higher 32 bits of multiplication in dest (signed * signed)
  • MULHU dest, src, src2 ; as above (but unsigned * unsigned)
  • MULHSU dest, src, src2 ; as above (but signed * unsigned)

Division

  • DIV dest, src1, src2 ; dest = src1 / src2 (with dest != src1 && dest != src2)
  • DIVU dest, src1, src2 ; same as above but unsigned
  • REM dest, src1, src2 ; dest = remainder of src1 / src2
  • REMU dest, src1, src2 ; same as above but unsigned

Have a look at the RISC V specification for the semantics of division by zero/overflow.

RV64I

Special RV64I Instructions

  • ADDIW dest, src, imm ; Sign extend 12 bit immediate, adds it to src, takes the lower 32 bits and sign extends that to 64 bits, which are then written into dest
  • {SLLIW,SRLIW,SRAIW} dest, src, imm ; Logical/Arithmetic shifts lower 32 bits by amount given by immediate. The upper 32 bits are set to 0 (not exactly described by RISC V specification, but that makes the most sense).
  • {ADDW, SUBW} dest, src1, src2 ; Addition/Subtraction of two registers, operates on lower 32 bits and sign extends the result to 64 bits, which are then written into dest
  • {SLLW, SRLW, SRAW} dest, src, shiftAmount ; Logical/Arithmetic as described above, but shift amount is specified by register

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