RISC V sample programs

These program snippets demonstrate basic functionality of this simulator. The snippets can also be found in the example-programs folder in the repository under similar names.

Simple Lightstrip

• RISC-V 32 bit
• Lightstrip component (memory address: 0; number of strips: 8)

; Config: lightstrip (8 strips, start address 0x0)
.section data ; Start a data section to define values in memory
strip: .resb 1
.equ startvalue, 0xff
.equ num_stripes, 8
.equ sleeptime, 500

.section text ; The code follows
start:
addi x1, x0, startvalue
sb x1, x0, 0
addi x2, x0, num_stripes
loop:
srli x1, x1, 1
sb x1, x0, 0
addi x2, x2, -1
simusleep sleeptime
bne x0, x2, loop
jal x0, start

Jumping Lightstrip

• RISC-V 32 bit
• Lightstrip component (memory address: 0; number of strips: 16)

; Config: lightstrip (16 strips, start address 0x0)
.section data
.resb 2
.equ strip, 0
.equ bars, 16
.equ sleept, 250

.section text
addi x1, x0, 1
addi x2, x0, 1
addi x3, x0, bars
addi x4, x0, 1

go_right:
slli x1, x1, 1
sw x1, x0, strip
addi x2, x2, 1
simusleep sleept
bne x3, x2, go_right
jal x0, go_left

go_left:
srli x1, x1, 1
sw x1, x0, strip
addi x2, x2, -1
simusleep sleept
bne x4, x2, go_left
jal x0, go_right

Seven-Segment counter

• RISC-V 32 bit
• seven-segment component (memory address: 0)

; Config seven-segment (start address 0x0)
.section data
.equ seg, 0
.resb 2
numbers: .byte 0b111111, 0b110, 0b1011011, 0b1001111, 0b1100110, 0b1101101,0b1111101,0b111,0b1111111,0b1101111

.section text
init:
addi x1, x0, 0
addi x2, x0, 10
main_loop:
jal x3, show_num
simusleep 250
addi x1, x1, 1
blt x1, x2, main_loop
addi x1, x0, 0
jal x0, main_loop

show_num:
lb x30, x1, numbers
sb x30, x0, seg
jalr x0, x3, 0

Lightstrip control with buttons

• RISC-V 32 bit
• arrow button input component (memory address: 0)
• lightstrip component (memory address: 4; number of strips: 8)

; Config: Pfeiltasten src=0
; Lightstrip 8 stripes; src = 4
.section data
.resb 5
.equ input, 0
.equ out, 4
.equ left, 0x3
.equ right, 0x1
.section text

init:
addi x1, x0, 1
sb x1, x0, out
addi x3, x0, left
addi x4, x0, right
loop:
lb x2, x0, input
beq x2, x3, shift_l
beq x2, x4, shift_r
end:
simusleep 100
jal x0, loop

shift_l:
srli x1, x1, 1
sb x1, x0, out
sb x0, x0, input
jal x0, end
shift_r:
slli x1, x1, 1
sb x1, x0, out
sb x0, x0, input
jal x0, end

Case changer

• RISC-V 32 bit
• console (memory address: 0, mode: array-based)

; Config: console at address 0x0
.section data
console: .byte "Some long text"
.byte 0 ; The obligatory zero byte

.section text
start:
addi x1, x0, 0
addi x4, x0, 0x20
loop:
jal x3, change_case
addi x1, x1, 1
simusleep 100
jal x0, loop

;index in x1
;working with x2
; return to x3
change_case:
lb x2, x1, console
beq x0, x2, end
beq x4, x2, change_case_end
xori x2, x2, 0b100000
sb x2, x1, console
change_case_end:
jalr x0, x3, 0

end:
nop ; Just to stop the execution
; simucrash "finished" would also be fine

strcpy

• RISC-V 32bit
• Console (memory address: 128, mode: array-based)

.section data
data: .byte "Some crazy long string to copy"
.equ  to, 0x80; = 128

.section text
loop:
lb x2, x1, data
beq x0, x2, end
sb x2, x1, to
addi x1,x1,1
jal x0, loop

end:
simucrash "finished!"