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Expand file tree Collapse file tree 6 files changed +34
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lines changed Original file line number Diff line number Diff line change @@ -210,6 +210,9 @@ export CELL_PAD_IN_SITES_DETAIL_PLACEMENT ?= 0
210210export ENABLE_DPO ?= 1
211211export DPO_MAX_DISPLACEMENT ?= 5 1
212212
213+ # Settings for Sizing
214+ export MATCH_CELL_FOOTPRINT ?= 0
215+
213216# Setup working directories
214217export DESIGN_NICKNAME ?= $(DESIGN_NAME )
215218
Original file line number Diff line number Diff line change @@ -113,8 +113,8 @@ if { [env_var_equals REMOVE_ABC_BUFFERS 1] } {
113113
114114# #### Restructure for timing #########
115115if { [env_var_equals RESYNTH_TIMING_RECOVER 1] } {
116- repair_design
117- repair_timing
116+ repair_design_helper
117+ repair_timing_helper
118118 # pre restructure area/timing report (ideal clocks)
119119 puts " Post synth-opt area"
120120 report_design_area
@@ -133,8 +133,8 @@ if { [env_var_equals RESYNTH_TIMING_RECOVER 1] } {
133133
134134 # post restructure area/timing report (ideal clocks)
135135 remove_buffers
136- repair_design
137- repair_timing
136+ repair_design_helper
137+ repair_timing_helper
138138
139139 puts " Post restructure-opt wns"
140140 report_worst_slack -max -digits 3
Original file line number Diff line number Diff line change @@ -51,8 +51,7 @@ proc global_route_helper {} {
5151 }
5252
5353 # Repair design using global route parasitics
54- puts " Perform buffer insertion..."
55- repair_design
54+ repair_design_helper
5655 if { $::env(DETAILED_METRICS) } {
5756 report_metrics 5 " global route post repair design"
5857 }
Original file line number Diff line number Diff line change @@ -21,18 +21,7 @@ if { ![env_var_exists_and_non_empty FOOTPRINT] } {
2121 }
2222}
2323
24- puts " Perform buffer insertion..."
25- set additional_args " "
26- if { [env_var_exists_and_non_empty CAP_MARGIN] && $::env(CAP_MARGIN) > 0.0} {
27- puts " Cap margin $::env(CAP_MARGIN) "
28- append additional_args " -cap_margin $::env(CAP_MARGIN) "
29- }
30- if { [env_var_exists_and_non_empty SLEW_MARGIN] && $::env(SLEW_MARGIN) > 0.0} {
31- puts " Slew margin $::env(SLEW_MARGIN) "
32- append additional_args " -slew_margin $::env(SLEW_MARGIN) "
33- }
34-
35- repair_design {*}$additional_args
24+ repair_design_helper
3625
3726if { [env_var_exists_and_non_empty TIE_SEPARATION] } {
3827 set tie_separation $env(TIE_SEPARATION)
Original file line number Diff line number Diff line change @@ -27,10 +27,23 @@ proc repair_timing_helper { {hold_margin 1} } {
2727 append_env_var additional_args SKIP_GATE_CLONING -skip_gate_cloning 0
2828 append_env_var additional_args SKIP_BUFFER_REMOVAL -skip_buffer_removal 0
2929 append_env_var additional_args SKIP_LAST_GASP -skip_last_gasp 0
30+ append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
3031 puts " repair_timing [ join $additional_args " " ] "
3132 repair_timing {*}$additional_args
3233}
3334
35+ proc repair_design_helper {} {
36+ puts " Perform buffer insertion and gate resizing..."
37+
38+ set additional_args " "
39+ append_env_var additional_args CAP_MARGIN -cap_margin 1
40+ append_env_var additional_args SLEW_MARGIN -slew_margin 1
41+ append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
42+ puts " repair_design [ join $additional_args " " ] "
43+
44+ repair_design {*}$additional_args
45+ }
46+
3447proc recover_power {} {
3548 if { $::env(RECOVER_POWER) == 0 } {
3649 return
@@ -40,7 +53,10 @@ proc recover_power {} {
4053 report_tns
4154 report_wns
4255 report_power
43- repair_timing -recover_power $::env(RECOVER_POWER)
56+ set additional_args " "
57+ append_env_var additional_args RECOVER_POWER -recover_power 1
58+ append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
59+ repair_timing {*}$additional_args
4460 report_tns
4561 report_wns
4662 report_power
Original file line number Diff line number Diff line change @@ -622,3 +622,11 @@ GLOBAL_ROUTE_ARGS:
622622 stages :
623623 - grt
624624 default : -congestion_iterations 30 -congestion_report_iter_step 5 -verbose
625+ MATCH_CELL_FOOTPRINT :
626+ description : >
627+ Enforce sizing operations to only swap cells that have the same layout boundary.
628+ stages :
629+ - floorplan
630+ - place
631+ - cts
632+ - route
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