synth: Rm .lib preprocess after tools improved

[openroad-ci]

No description provided.

[povik]

Supersedes #1807, #2619

Closes #3241

[maliberty]

Why are you adding a dependency here? @oharboe ok?

[oharboe]

Long story, but I dont want these dependencies to be bazel artifacts.

This step massages exisiting artifacts and produces e.g. merged.lib, which is quite large.

[povik]

Because most of the dependencies grouped as yosys-dependencies are in fact required by do-yosys

[povik]

but I dont want these dependencies to be bazel artifacts.

@oharboe I'm not sure what that implies, can we add the make dependency?

[maliberty]

I'm glad to be rid of this cruft.

[oharboe]

Reviewing on the road: this is a great simplification!

There is a chance it will break bazel-orfs, but as long as we can collaborate on this post merge, I say merge.

[maliberty]

A few test failures to address

[povik]

The failures are due to abc failing to read libraries produced with sta's write_timing_model. I've posted a fix upstream berkeley-abc/abc#437

[oharboe]

The failures are due to abc failing to read libraries produced with sta's write_timing_model. I've posted a fix upstream berkeley-abc/abc#437

Merged.

Purely for my planning purposes, I have to delete some cruft in bazel-orfs when this is merged, what are the next steps and when will this merge? After next yosys update?

[povik]

Yosys needs to update their abc, and we need to update our yosys. I’m guessing it will take 2 or 6 weeks.

[povik]

designs/gf180/aes-hybrid/rules-base.json updates:

Metric	Old	New	Type
synth__design__instance__area__stdcell	624425.81	493531.52	Tighten
placeopt__design__instance__area	798562	657615	Tighten
placeopt__design__instance__count__stdcell	22568	22088	Tighten
globalroute__antenna_diodes_count	3	2	Tighten
detailedroute__route__wirelength	1623163	1503800	Tighten
detailedroute__antenna_diodes_count	5	9	Failing
finish__timing__setup__ws	-1.16	-1.35	Failing
finish__design__instance__area	803898	779709	Tighten

[maliberty]

why does removing the preprocessing change the results?

[povik]

I'm not sure. Should I find out where the divergence starts?

[maliberty]

I think so if it is unexplained.

[povik]

I've found the first divergence is picking different technology flops to map to. Previously synthesis would use 9t cells and now it uses 7t. I'm not sure why it chose 9t previously since Yosys should pick those with lower area.

74401c74401
<   cell \gf180mcu_fd_sc_mcu9t5v0__dffq_2 \u0.w[3][12]$_DFF_P_
---
>   cell \gf180mcu_fd_sc_mcu7t5v0__dffq_2 \u0.w[3][12]$_DFF_P_

[povik]

The 7t flop has lower area and the same number of pins.

attribute \area "68.051200"
module \gf180mcu_fd_sc_mcu7t5v0__dffq_2
  wire output 3 \Q
  wire input 2 \D
  wire input 1 \CLK
end

attribute \area "84.672000"
module \gf180mcu_fd_sc_mcu9t5v0__dffq_2
  wire output 3 \Q
  wire input 2 \D
  wire input 1 \CLK
end

[povik]

I think I understand it now. Previously only the first library from LIB_FILES would get used in synthesis. asap7 worked around this by having the merge step at the platform level. There was no such merge step for gf180/aes-hybrid despite supplying both the 9t and 7t libraries.

[povik]

@maliberty I think all is good to review and merge.

[maliberty]

That test case is a hack as there is no public PDK with hybrid rows.

[rovinski]

Not sure I can convey how happy it makes me to see this merged 😅
Thank you!!!

[povik]

Thanks to you and @widlarizer for prior work in this direction.

[oharboe]

bazel-orfs updated

😌