Do not write physical-only cells on the output verilog file in the final stage.#3480
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maliberty merged 3 commits intoThe-OpenROAD-Project:masterfrom Sep 9, 2025
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…nal stage. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
maliberty
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Sep 9, 2025
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Physical-only cells should not be present in the generated verilog file.
is_physical_only_masterandfind_physical_only_mastersinutil.tcl.-remove_cells <master_list>argument in thewrite_verilog.This is an alternative solution to the netlist iteration method (The-OpenROAD-Project/OpenROAD#8256), which has the side effect of introducing leakage power errors.