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synth: add SYNTH_MOCK_LARGE_MEMORIES #3621

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Merged
maliberty merged 10 commits into from
Nov 11, 2025
Merged

synth: add SYNTH_MOCK_LARGE_MEMORIES #3621

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06042cd
synth: add SYNTH_MOCK_LARGE_MEMORIES
oharboe Oct 27, 2025
9d98e8f
synth: support SYNTH_MOCK_LARGE_MEMORIES
povik Oct 27, 2025
867f895
synth: Fix foreach doing unwanted substitutions
povik Nov 7, 2025
04bae58
Merge remote-tracking branch 'origin/master' into HEAD
oharboe Nov 7, 2025
bf47644
lint nits
oharboe Nov 7, 2025
e511371
synth: mock memories doc and example
oharboe Nov 8, 2025
916b9de
synth: keep mocked memories by default
oharboe Nov 9, 2025
da6546c
synth: endpoint slack histogram for mocked memories
oharboe Nov 9, 2025
772ba49
docs: add some tips on large designs
oharboe Nov 10, 2025
2f84d03
docs: add some tips on large designs, review followup
oharboe Nov 10, 2025
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5 changes: 1 addition & 4 deletions flow/designs/sky130hd/microwatt/config.mk
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Expand Up @@ -36,7 +36,4 @@ export SETUP_SLACK_MARGIN = 0.2
# GRT non-default config
export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl

# This is high, some SRAMs should probably be converted
# to real SRAMs and not instantiated as flops
export SYNTH_MEMORY_MAX_BITS = 42000

export SYNTH_MOCK_LARGE_MEMORIES = 1
14 changes: 14 additions & 0 deletions flow/scripts/synth.tcl
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Expand Up @@ -55,6 +55,20 @@ if { !$::env(SYNTH_HIERARCHICAL) } {
synth -flatten -run coarse:fine {*}$synth_full_args
}


if { $::env(SYNTH_MOCK_LARGE_MEMORIES) } {
foreach module [get_modules] {
foreach mem [get_memories $module] {
set size [memory_get $module $mem SIZE]

if {$size > $::env(SYNTH_MEMORY_MAX_BITS)} {
memory_set $module $mem SIZE 1
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@povik povik Oct 27, 2025

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@oharboe Is memory_set a hypothetical command?

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@povik povik Oct 27, 2025

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I see there are other dreamed up commands. Let me see if this can be implemented using real commands

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@oharboe oharboe Oct 27, 2025

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Yes. In ChatGPT's defense it did say that it dreamt up these commands and then it looked for alternatives.

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@povik povik Oct 27, 2025

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I offer this for testing:

memory_collect
foreach path [tee -q -s result.string select -list t:\$mem_v2] {
	set index [string first "/" $path]
	set module [string range $path 0 [expr {$index - 1}]]
	set instance [string range $path [expr {$index + 1}] end]

	set width [rtlil::get_param -uint $module $instance WIDTH]
	set size [rtlil::get_param -uint $module $instance SIZE]
	set nbits [expr $width * $size]
	puts "Memory $path has dimensions $size x $width = $nbits"
	if {$nbits > $::env(SYNTH_MEMORY_MAX_BITS)} {
		rtlil::set_param -uint $module $instance SIZE 1
		puts "Shrunk memory $path from $size rows to 1"
	}
}

puts "Shrunk memory $mem in module $module from $size to 1"
}
}
}
}

json -o $::env(RESULTS_DIR)/mem.json
# Run report and check here so as to fail early if this synthesis run is doomed
exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py \
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16 changes: 16 additions & 0 deletions flow/scripts/variables.yaml
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Expand Up @@ -177,6 +177,22 @@ SYNTH_MEMORY_MAX_BITS:
default: 4096
stages:
- synth
SYNTH_MOCK_LARGE_MEMORIES:
description: >
Reduce memories larger than SYNTH_MEMORY_MAX_BITS to 1 row.

This is useful to separate the concern of instantiating and placing
memories from investigating other issues with a design.

Memories with a single 1 row will of course have unrealistically good
timing and area characteristics, but timing will still correctly terminate
in a register.
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@povik povik Nov 7, 2025

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Let me also point out a concern that some of the logic driving the address input on the RAM will be optimized out when we override the RAM size

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@oharboe oharboe Nov 7, 2025

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Hmmm... I think these sort of downstream consequences are evident to anyone skilled in the art given the warning in the doc?

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@povik povik Nov 7, 2025

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Possibly. In my experience people are surprised by what can get optimized out when they mock something in their design

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@oharboe oharboe Nov 7, 2025

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I see.... The idea is that whatever problems remain after mocking, they are real place/route/timing closure problems and worth sorting out while waiting for real RAM or some more accurate fake RAM.

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@oharboe oharboe Nov 7, 2025

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Perhaps a more stern comment to the effect "you asked for it and you deserve the result" would be helpful, but I think it is fine the way it is.


Also, large port memories, typically register files, will still have the
retain a lot of the port logic that can be useful to investigate issues.
default: 0
stages:
- synth
SYNTH_HDL_FRONTEND:
description: >
Select an alternative language frontend to ingest the design. Available option
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