synth: add SYNTH_MOCK_LARGE_MEMORIES

docs/user/FlowVariables.md

@@ -245,6 +245,7 @@ configuration file.
 | <a name="SYNTH_KEEP_MODULES"></a>SYNTH_KEEP_MODULES| Mark modules to keep from getting removed in flattening.| |
 | <a name="SYNTH_MEMORY_MAX_BITS"></a>SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096|
 | <a name="SYNTH_MINIMUM_KEEP_SIZE"></a>SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0|
+| <a name="SYNTH_MOCK_LARGE_MEMORIES"></a>SYNTH_MOCK_LARGE_MEMORIES| Reduce memories larger than SYNTH_MEMORY_MAX_BITS to 1 row. This is useful to separate the concern of instantiating and placing memories from investigating other issues with a design. Memories with a single 1 row will of course have unrealistically good timing and area characteristics, but timing will still correctly terminate in a register. Also, large port memories, typically register files, will still have the retain a lot of the port logic that can be useful to investigate issues.| 0|
 | <a name="SYNTH_NETLIST_FILES"></a>SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| |
 | <a name="SYNTH_OPT_HIER"></a>SYNTH_OPT_HIER| Optimize constants across hierarchical boundaries.| |
 | <a name="SYNTH_RETIME_MODULES"></a>SYNTH_RETIME_MODULES| *This is an experimental option and may cause adverse effects.* *No effort has been made to check if the retimed RTL is logically equivalent to the non-retimed RTL.* List of modules to apply automatic retiming to. These modules must not get dissolved and as such they should either be the top module or be included in SYNTH_KEEP_MODULES. The main use case is to quickly identify if performance can be improved by manually retiming the input RTL. Retiming will treat module ports like register endpoints/startpoints. The objective function of retiming isn't informed by SDC, even the clock period is ignored. As such, retiming will optimize for best delay at potentially high register number cost. Automatic retiming can produce suboptimal results as its timing model is crude and it doesn't find the optimal distribution of registers on long pipelines. See OR discussion #8080.| |
@@ -284,6 +285,7 @@ configuration file.
 - [SYNTH_KEEP_MODULES](#SYNTH_KEEP_MODULES)
 - [SYNTH_MEMORY_MAX_BITS](#SYNTH_MEMORY_MAX_BITS)
 - [SYNTH_MINIMUM_KEEP_SIZE](#SYNTH_MINIMUM_KEEP_SIZE)
+- [SYNTH_MOCK_LARGE_MEMORIES](#SYNTH_MOCK_LARGE_MEMORIES)
 - [SYNTH_NETLIST_FILES](#SYNTH_NETLIST_FILES)
 - [SYNTH_OPT_HIER](#SYNTH_OPT_HIER)
 - [SYNTH_RETIME_MODULES](#SYNTH_RETIME_MODULES)

flow/designs/sky130hd/microwatt/config.mk

@@ -36,7 +36,4 @@ export SETUP_SLACK_MARGIN = 0.2
 # GRT non-default config
 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
 
-# This is high, some SRAMs should probably be converted
-# to real SRAMs and not instantiated as flops
-export SYNTH_MEMORY_MAX_BITS = 42000
-
+export SYNTH_MOCK_LARGE_MEMORIES = 1

flow/scripts/synth.tcl

@@ -55,6 +55,26 @@ if { !$::env(SYNTH_HIERARCHICAL) } {
   synth -flatten -run coarse:fine {*}$synth_full_args
 }
 
+
+if { $::env(SYNTH_MOCK_LARGE_MEMORIES) } {
+  memory_collect
+  set select [tee -q -s result.string select -list t:\$mem_v2]
+  foreach path [split [string trim $select] "\n"] {
+    set index [string first "/" $path]
+    set module [string range $path 0 [expr { $index - 1 }]]
+    set instance [string range $path [expr { $index + 1 }] end]
+
+    set width [rtlil::get_param -uint $module $instance WIDTH]
+    set size [rtlil::get_param -uint $module $instance SIZE]
+    set nbits [expr $width * $size]
+    puts "Memory $path has dimensions $size x $width = $nbits"
+    if { $nbits > $::env(SYNTH_MEMORY_MAX_BITS) } {
+      rtlil::set_param -uint $module $instance SIZE 1
+      puts "Shrunk memory $path from $size rows to 1"
+    }
+  }
+}
+
 json -o $::env(RESULTS_DIR)/mem.json
 # Run report and check here so as to fail early if this synthesis run is doomed
 exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py \

flow/scripts/variables.yaml

@@ -177,6 +177,22 @@ SYNTH_MEMORY_MAX_BITS:
   default: 4096
   stages:
     - synth
+SYNTH_MOCK_LARGE_MEMORIES:
+  description: >
+    Reduce memories larger than SYNTH_MEMORY_MAX_BITS to 1 row.
+
+    This is useful to separate the concern of instantiating and placing
+    memories from investigating other issues with a design.
+
+    Memories with a single 1 row will of course have unrealistically good
+    timing and area characteristics, but timing will still correctly terminate
+    in a register.
+
+    Also, large port memories, typically register files, will still have the
+    retain a lot of the port logic that can be useful to investigate issues.
+  default: 0
+  stages:
+    - synth
 SYNTH_HDL_FRONTEND:
   description: >
     Select an alternative language frontend to ingest the design. Available option