ODB: Allow multiple chip def reads

include/ord/Design.h

@@ -130,8 +130,7 @@ class Design
   void readDef(const std::string& file_name,
                bool continue_on_errors = false,
                bool floorplan_init = false,
-               bool incremental = false,
-               bool child = false);
+               bool incremental = false);
   void link(const std::string& design_name);
 
   void readDb(std::istream& stream);

include/ord/OpenRoad.hh

@@ -17,6 +17,7 @@ class dbDatabase;
 class dbBlock;
 class dbTech;
 class dbLib;
+class dbChip;
 class Point;
 class Rect;
 }  // namespace odb
@@ -190,11 +191,10 @@ class OpenRoad
                bool make_library);
 
   void readDef(const char* filename,
-               odb::dbTech* tech,
+               odb::dbChip* chip,
                bool continue_on_errors,
                bool floorplan_init,
-               bool incremental,
-               bool child);
+               bool incremental);
 
   void writeLef(const char* filename);
 

src/Design.cc

@@ -54,8 +54,7 @@ void Design::readVerilog(const std::string& file_name)
 void Design::readDef(const std::string& file_name,
                      bool continue_on_errors,  // = false
                      bool floorplan_init,      // = false
-                     bool incremental,         // = false
-                     bool child                // = false
+                     bool incremental          // = false
 )
 {
   if (floorplan_init && incremental) {
@@ -67,12 +66,12 @@ void Design::readDef(const std::string& file_name,
   if (tech_->getDB()->getTech() == nullptr) {
     getLogger()->error(utl::ORD, 102, "No technology has been read.");
   }
-  getOpenRoad()->readDef(file_name.c_str(),
-                         tech_->getDB()->getTech(),
-                         continue_on_errors,
-                         floorplan_init,
-                         incremental,
-                         child);
+  auto chip = tech_->getDB()->getChip();
+  if (chip == nullptr) {
+    chip = odb::dbChip::create(tech_->getDB(), tech_->getDB()->getTech());
+  }
+  getOpenRoad()->readDef(
+      file_name.c_str(), chip, continue_on_errors, floorplan_init, incremental);
 }
 
 void Design::link(const std::string& design_name)

src/OpenRoad.cc

@@ -329,14 +329,12 @@ void OpenRoad::readLef(const char* filename,
 }
 
 void OpenRoad::readDef(const char* filename,
-                       dbTech* tech,
+                       dbChip* chip,
                        bool continue_on_errors,
                        bool floorplan_init,
-                       bool incremental,
-                       bool child)
+                       bool incremental)
 {
-  if (!floorplan_init && !incremental && !child && db_->getChip()
-      && db_->getChip()->getBlock()) {
+  if (!floorplan_init && !incremental && chip && chip->getBlock()) {
     logger_->info(ORD, 48, "Loading an additional DEF.");
   }
 
@@ -354,12 +352,7 @@ void OpenRoad::readDef(const char* filename,
   if (continue_on_errors) {
     def_reader.continueOnErrors();
   }
-  if (child) {
-    auto parent = db_->getChip()->getBlock();
-    def_reader.createBlock(parent, search_libs, filename, tech);
-  } else {
-    def_reader.createChip(search_libs, filename, tech);
-  }
+  def_reader.readChip(search_libs, filename, chip);
 }
 
 static odb::defout::Version stringToDefVersion(const string& version)

src/OpenRoad.i

@@ -311,26 +311,14 @@ read_lef_cmd(const char *filename,
 
 void
 read_def_cmd(const char *filename,
-             const char* tech_name,
              bool continue_on_errors,
              bool floorplan_init,
              bool incremental,
-             bool child)
+             odb::dbChip* chip)
 {
   OpenRoad *ord = getOpenRoad();
-  auto* db = ord->getDb();
-  dbTech* tech;
-  if (tech_name[0] != '\0') {
-    tech = db->findTech(tech_name);
-  } else {
-    tech = db->getTech();
-  }
-  if (!tech) {
-    auto logger = getLogger();
-    logger->error(utl::ORD, 52, "Technology {} not found", tech_name);
-  }
-  ord->readDef(filename, tech, continue_on_errors,
-               floorplan_init, incremental, child);
+  ord->readDef(filename, chip, continue_on_errors,
+               floorplan_init, incremental);
 }
 
 void

src/OpenRoad.tcl

@@ -38,15 +38,16 @@ proc read_lef { args } {
   ord::read_lef_cmd $filename $lib_name $tech_name $make_tech $make_lib
 }
 
-sta::define_cmd_args "read_def" {[-floorplan_initialize|-incremental|-child]\
+sta::define_cmd_args "read_def" {[-floorplan_initialize|-incremental]\
                                    [-continue_on_errors]\
                                    [-tech name] \
+                                   [-chip chip_name] \
                                    filename}
 
 proc read_def { args } {
-  sta::parse_key_args "read_def" args keys {-tech} \
+  sta::parse_key_args "read_def" args keys {-tech -chip} \
     flags {-floorplan_initialize -incremental \
-           -order_wires -continue_on_errors -child}
+           -order_wires -continue_on_errors}
   sta::check_argc_eq1 "read_def" $args
   set filename [file nativename [lindex $args 0]]
   if { ![file exists $filename] } {
@@ -55,25 +56,41 @@ proc read_def { args } {
   if { ![file readable $filename] || ![file isfile $filename] } {
     utl::error "ORD" 4 "$filename is not readable."
   }
-  set tech_name ""
   if { [info exists keys(-tech)] } {
     set tech_name $keys(-tech)
+    set tech [[ord::get_db] findTech $tech_name]
+    if { $tech == "NULL" } {
+      utl::error ORD 52 "Technology $tech_name not found."
+    }
   } elseif { ![ord::db_has_tech] } {
     utl::error "ORD" 5 "No technology has been read."
+  } else {
+    set tech [[ord::get_db] getTech]
   }
   if { [info exists flags(-order_wires)] } {
     utl::warn "ORD" 33 "-order_wires is deprecated."
   }
   set continue_on_errors [info exists flags(-continue_on_errors)]
   set floorplan_init [info exists flags(-floorplan_initialize)]
   set incremental [info exists flags(-incremental)]
-  set child [info exists flags(-child)]
-  if { $floorplan_init + $incremental + $child > 1 } {
-    utl::error ORD 16 "Options -incremental, -floorplan_initialization,\
-      and -child are mutually exclusive."
+  if { $floorplan_init + $incremental > 1 } {
+    utl::error ORD 16 "Options -incremental and -floorplan_initialization\
+      are mutually exclusive."
+  }
+  if { [info exists keys(-chip)] } {
+    set chip [[ord::get_db] findChip $keys(-chip)]
+    if { $chip == "NULL" } {
+      utl::error ORD 21 "Chip $keys(-chip) not found."
+    }
+  } else {
+    if { [[ord::get_db] getChip] == "NULL" } {
+      set chip [odb::dbChip_create [ord::get_db] $tech]
+    } else {
+      set chip [[ord::get_db] getChip]
+    }
   }
-  ord::read_def_cmd $filename $tech_name $continue_on_errors $floorplan_init \
-    $incremental $child
+  ord::read_def_cmd $filename $continue_on_errors $floorplan_init \
+    $incremental $chip
 }
 
 sta::define_cmd_args "write_def" {[-version version] filename}

src/cts/test/array.tcl

@@ -19,7 +19,7 @@ read_lef array_tile.lef
 
 set db [ord::get_db]
 set tech [ord::get_db_tech]
-set chip [odb::dbChip_create $db]
+set chip [odb::dbChip_create $db $tech]
 set block [odb::dbBlock_create $chip "top"]
 $block setDefUnits 2000
 

src/cts/test/array_dummy.tcl

@@ -19,7 +19,7 @@ read_lef array_tile.lef
 
 set db [ord::get_db]
 set tech [ord::get_db_tech]
-set chip [odb::dbChip_create $db]
+set chip [odb::dbChip_create $db $tech]
 set block [odb::dbBlock_create $chip "top"]
 $block setDefUnits 2000
 

src/cts/test/array_full_flow.tcl

@@ -19,7 +19,7 @@ read_lef array_tile.lef
 
 set db [ord::get_db]
 set tech [ord::get_db_tech]
-set chip [odb::dbChip_create $db]
+set chip [odb::dbChip_create $db $tech]
 set block [odb::dbBlock_create $chip "top"]
 $block setDefUnits 2000
 

src/cts/test/array_ins_delay.tcl

@@ -19,7 +19,7 @@ read_lef array_tile.lef
 
 set db [ord::get_db]
 set tech [ord::get_db_tech]
-set chip [odb::dbChip_create $db]
+set chip [odb::dbChip_create $db $tech]
 set block [odb::dbBlock_create $chip "top"]
 $block setDefUnits 2000
 

src/cts/test/array_no_blockages.tcl

@@ -19,7 +19,7 @@ read_lef array_tile.lef
 
 set db [ord::get_db]
 set tech [ord::get_db_tech]
-set chip [odb::dbChip_create $db]
+set chip [odb::dbChip_create $db $tech]
 set block [odb::dbBlock_create $chip "top"]
 $block setDefUnits 2000
 

src/cts/test/array_repair_clock_nets.tcl

@@ -19,7 +19,7 @@ read_lef array_tile.lef
 
 set db [ord::get_db]
 set tech [ord::get_db_tech]
-set chip [odb::dbChip_create $db]
+set chip [odb::dbChip_create $db $tech]
 set block [odb::dbBlock_create $chip "top"]
 $block setDefUnits 2000
 

src/cts/test/cts-helpers.tcl

@@ -7,10 +7,11 @@ proc make_array {
   { clock_gate -1 }
 } {
   set db [ord::get_db]
-  set chip [odb::dbChip_create $db]
+  set tech [$db getTech]
+  set chip [odb::dbChip_create $db $tech]
   set block [odb::dbBlock_create $chip "multi_sink"]
   set master [$db findMaster "DFF_X1"]
-  set tech [$db getTech]
+
   set layer [$tech findLayer "metal6"]
   set min_width [$layer getWidth]
 

src/cts/test/cts_helpers.py

@@ -6,10 +6,11 @@
 proc make_array { sinks { width 200000 } { height 200000 } \
                       { clock_gate -1 } } {
   set db [ord::get_db]
-  set chip [odb::dbChip_create $db]
+  set tech [$db getTech]
+  set chip [odb::dbChip_create $db $tech]
   set block [odb::dbBlock_create $chip "multi_sink"]
   set master [$db findMaster "DFF_X1"]
-  set tech [$db getTech]
+
   set layer [$tech findLayer "metal6"]
   set min_width [$layer getWidth]
 

src/dbSta/src/dbReadVerilog.cc

@@ -251,7 +251,7 @@ void Verilog2db::makeBlock()
 {
   dbChip* chip = db_->getChip();
   if (chip == nullptr) {
-    chip = dbChip::create(db_);
+    chip = dbChip::create(db_, db_->getTech());
   }
   block_ = chip->getBlock();
   if (block_) {
@@ -275,10 +275,9 @@ void Verilog2db::makeBlock()
   } else {
     const char* design
         = network_->name(network_->cell(network_->topInstance()));
-    block_ = dbBlock::create(
-        chip, design, db_->getTech(), network_->pathDivider());
+    block_ = dbBlock::create(chip, design, network_->pathDivider());
   }
-  dbTech* tech = db_->getTech();
+  dbTech* tech = chip->getTech();
   block_->setDefUnits(tech->getLefUnits());
   block_->setBusDelimiters('[', ']');
 }
@@ -1111,14 +1110,14 @@ void Verilog2db::makeUnusedBlock(const char* name)
 {
   dbChip* chip = db_->getChip();
   if (chip == nullptr) {
-    chip = dbChip::create(db_);
+    chip = dbChip::create(db_, db_->getTech());
   }
   // Create a child block
   if (top_block_ == nullptr) {
     top_block_ = chip->getBlock();
   }
-  dbTech* tech = db_->getTech();
-  block_ = dbBlock::create(top_block_, name, tech, network_->pathDivider());
+  dbTech* tech = chip->getTech();
+  block_ = dbBlock::create(top_block_, name, network_->pathDivider());
   block_->setDefUnits(tech->getLefUnits());
   block_->setBusDelimiters('[', ']');
   debugPrint(logger_,

src/dbSta/test/cpp/TestHconn.cpp

@@ -301,7 +301,7 @@ class TestHconn : public ::testing::Test
     db_->setLogger(&logger_);
 
     // create a chain consisting of 4 buffers
-    odb::dbChip* chip = odb::dbChip::create(db_.get());
+    odb::dbChip* chip = odb::dbChip::create(db_.get(), db_->getTech());
     block_ = odb::dbBlock::create(chip, "top");
     db_network_->setBlock(block_);
     block_->setDieArea(odb::Rect(0, 0, 1000, 1000));

src/dpl/test/dpl_test.cc

@@ -26,8 +26,8 @@ class OpendpTest : public ::testing::Test
                                     "sky130hd/sky130_fd_sc_hd_merged.lef"),
         &odb::dbLib::destroy);
 
-    chip_ = OdbUniquePtr<odb::dbChip>(odb::dbChip::create(db_.get()),
-                                      &odb::dbChip::destroy);
+    chip_ = OdbUniquePtr<odb::dbChip>(
+        odb::dbChip::create(db_.get(), db_->getTech()), &odb::dbChip::destroy);
     block_ = OdbUniquePtr<odb::dbBlock>(
         odb::dbBlock::create(chip_.get(), "top"), &odb::dbBlock::destroy);
     block_->setDefUnits(lib_->getTech()->getLefUnits());

src/drt/test/fixture.cpp

@@ -262,7 +262,7 @@ void Fixture::makeDesign()
   odb::dbTech* tech = odb::dbTech::create(db_, "tech");
   odb::dbTechLayer::create(tech, "L1", dbTechLayerType::MASTERSLICE);
   odb::dbLib::create(db_, "lib1", tech, ',');
-  odb::dbChip* chip = odb::dbChip::create(db_);
+  odb::dbChip* chip = odb::dbChip::create(db_, tech);
   odb::dbBlock::create(chip, "simple_block");
 }
 

src/gpl/test/clust02.tcl

@@ -16,7 +16,7 @@ read_lef ./4BitTrayH2W2/asap7sc7p5t_DFFHQNH2V2X.lef
 read_lib ./4BitTrayH2W2/asap7sc7p5t_DFFHQNH2V2X_LVT_TT_nldm_FAKE.lib
 
 set db [ord::get_db]
-set chip [odb::dbChip_create $db]
+set chip [odb::dbChip_create $db [$db getTech]]
 set block [odb::dbBlock_create $chip "top"]
 $block setDefUnits 1000
 

src/gpl/test/clust03.tcl

@@ -7,7 +7,7 @@ read_lef ./SingleBit/asap7sc7p5t_28_L_1x_220121a.lef
 read_lib ./SingleBit/asap7sc7p5t_SEQ_LVT_TT_nldm_220123.lib
 
 set db [ord::get_db]
-set chip [odb::dbChip_create $db]
+set chip [odb::dbChip_create $db [$db getTech]]
 set block [odb::dbBlock_create $chip "top"]
 $block setDefUnits 1000
 

src/mpl/test/cpp/MplTest.h

@@ -24,7 +24,7 @@ class MplTest : public ::testing::Test
     odb::dbTech::create(db_.get(), "tech");
     odb::dbLib::create(db_.get(), "lib", db_->getTech(), ',');
 
-    odb::dbChip::create(db_.get());
+    odb::dbChip::create(db_.get(), db_->getTech());
 
     odb::dbBlock::create(db_->getChip(), "block");
     db_->getChip()->getBlock()->setDieArea(