cnn

designs/asap7/cnn/config.mk

@@ -0,0 +1,29 @@
+export DESIGN_NICKNAME ?= cnn
+export DESIGN_NAME = cnn
+export PLATFORM    = asap7
+
+#export SYNTH_HIERARCHICAL ?= 1
+
+#export SYNTH_MINIMUM_KEEP_SIZE ?= 10000
+
+export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/cnn/*.v))
+export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/cnn/constraint.sdc
+
+ifeq ($(BLOCKS),)
+	export ADDITIONAL_LEFS = $(sort $(wildcard $(DESIGN_HOME)/src/cnn/*.lef))
+	export ADDITIONAL_LIBS = $(sort $(wildcard $(DESIGN_HOME)/src/cnn/*.lib))
+endif
+
+#export CORE_UTILIZATION       = 40
+export DIE_AREA = 0 0 600 600
+export CORE_AREA = 10 10 590 590 
+#
+#export PLACE_DENSITY_LB_ADDON = 0.10
+
+#export IO_CONSTRAINTS     = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl
+#export MACRO_PLACE_HALO    = 2 2
+
+#export TNS_END_PERCENT   = 100
+#
+#export CTS_CLUSTER_SIZE = 10
+#export CTS_CLUSTER_DIAMETER = 50

designs/asap7/cnn/constraint.sdc

@@ -0,0 +1,14 @@
+current_design cnn
+
+set clk_name clk
+set clk_port_name CLK
+set clk_period 1500
+set clk_io_pct 0.125
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [all_inputs -no_clocks]
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

designs/asap7/cnn/rules-base.json

@@ -0,0 +1,70 @@
+{
+    "synth__design__instance__area__stdcell": {
+        "value": 2947.89,
+        "compare": "<="
+    },
+    "constraints__clocks__count": {
+        "value": 1,
+        "compare": "=="
+    },
+    "placeopt__design__instance__area": {
+        "value": 3109,
+        "compare": "<="
+    },
+    "placeopt__design__instance__count__stdcell": {
+        "value": 11777,
+        "compare": "<="
+    },
+    "detailedplace__design__violations": {
+        "value": 0,
+        "compare": "=="
+    },
+    "cts__design__instance__count__setup_buffer": {
+        "value": 1024,
+        "compare": "<="
+    },
+    "cts__design__instance__count__hold_buffer": {
+        "value": 1024,
+        "compare": "<="
+    },
+    "globalroute__antenna_diodes_count": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__route__wirelength": {
+        "value": 83651,
+        "compare": "<="
+    },
+    "detailedroute__route__drc_errors": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna__violating__nets": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna_diodes_count": {
+        "value": 5,
+        "compare": "<="
+    },
+    "finish__timing__setup__ws": {
+        "value": -44.21,
+        "compare": ">="
+    },
+    "finish__design__instance__area": {
+        "value": 3180,
+        "compare": "<="
+    },
+    "finish__timing__drv__setup_violation_count": {
+        "value": 512,
+        "compare": "<="
+    },
+    "finish__timing__drv__hold_violation_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "finish__timing__wns_percent_delay": {
+        "value": -10.0,
+        "compare": ">="
+    }
+}

designs/src/cnn/fakeram_asap7/fakeram_w16_l32768/fakeram_w16_l32768.bb.v

@@ -0,0 +1,34 @@
+module fakeram_w16_l32768
+(
+   rw0_wd_in,
+   rw0_we_in,
+   rw0_rd_out,
+   rw0_clk,
+   rw0_ce_in,
+   rw0_addr_in,
+   rw1_wd_in,
+   rw1_we_in,
+   rw1_rd_out,
+   rw1_clk,
+   rw1_ce_in,
+   rw1_addr_in,
+);
+   parameter BITS = 16;
+   parameter WORD_DEPTH = 16384;
+   parameter ADDR_WIDTH = 14;
+   parameter corrupt_mem_on_X_p = 1;
+
+   input                    rw0_clk;
+   input                    rw0_ce_in;
+   input  [ADDR_WIDTH-1:0]  rw0_addr_in;
+   output reg [BITS-1:0]    rw0_rd_out;
+   input                    rw0_we_in;
+   input  [BITS-1:0]        rw0_wd_in;
+   input                    rw1_clk;
+   input                    rw1_ce_in;
+   input  [ADDR_WIDTH-1:0]  rw1_addr_in;
+   output reg [BITS-1:0]    rw1_rd_out;
+   input                    rw1_we_in;
+   input  [BITS-1:0]        rw1_wd_in;
+
+endmodule