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[WIP] Fix JSL instruction not picking middle address byte #18

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[WIP] Fix JSL instruction not picking middle address byte #18

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85c5194
Initial plan
Copilot Oct 14, 2025
f45fc66
Fix JSL instruction to correctly read 3-byte address
Copilot Oct 14, 2025
f9607d2
Add test case for JSL instruction
Copilot Oct 14, 2025
d92e9ef
Address code review feedback for JSL test
Copilot Oct 14, 2025
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2 changes: 1 addition & 1 deletion ext/firmware
Open in desktop
Submodule firmware updated 11 files
+2 −1 CMakeLists.txt
+1 −0 src/CMakeLists.txt
+8 −9 src/ria/cgia/cgia.c
+3 −3 src/ria/main.c
+4 −2 src/ria/main.h
+2 −1 src/ria/mon/hlp.c
+20 −24 src/ria/sys/aud.c
+17 −1 src/ria/sys/bus.c
+36 −27 src/ria/sys/ext.c
+4 −2 src/ria/sys/ext.h
+10 −3 src/ria/sys/out.c
2 changes: 1 addition & 1 deletion ext/imgui
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Submodule imgui updated 129 files
2 changes: 1 addition & 1 deletion ext/sokol
Open in desktop
Submodule sokol updated 23 files
+6 −2 .github/workflows/gen_bindings.yml
+432 −0 CHANGELOG.md
+1 −1 README.md
+12 −2 bindgen/gen_all.py
+9 −12 bindgen/gen_c3.py
+55 −6 bindgen/gen_d.py
+14 −31 bindgen/gen_zig.py
+1,345 −692 sokol_app.h
+7 −0 sokol_audio.h
+4,142 −3,521 sokol_gfx.h
+1 −1 sokol_log.h
+4 −0 tests/ext/CMakeLists.txt
+1 −0 tests/ext/nuklear.c
+5,555 −3,968 tests/ext/nuklear.h
+476 −861 tests/functional/sokol_gfx_test.c
+21 −15 tests/functional/sokol_gl_test.c
+35 −13 util/sokol_debugtext.h
+33 −16 util/sokol_fontstash.h
+1,062 −834 util/sokol_gfx_imgui.h
+42 −32 util/sokol_gl.h
+450 −287 util/sokol_imgui.h
+51 −29 util/sokol_nuklear.h
+71 −52 util/sokol_spine.h
2 changes: 1 addition & 1 deletion ext/sokol-tools-bin
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Submodule sokol-tools-bin updated 8 files
+ − bin/linux/sokol-shdc
+ − bin/linux_arm64/sokol-shdc
+ − bin/osx/sokol-shdc
+ − bin/osx_arm64/sokol-shdc
+ − bin/win32/sokol-shdc.exe
+69 −27 build.zig
+22 −0 testdata/triangle.glsl
+90 −0 testdata/triangle.glsl.zig
14 changes: 7 additions & 7 deletions src/chips/w65c816s.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1240,13 +1240,13 @@ uint64_t w65816_tick(w65816_t* c, uint64_t pins) {
/* JSL a */
case (0x22<<4)|0: _VPA();_SA(c->PC++);break;
case (0x22<<4)|1: _VPA();_SA(c->PC++);c->AD=_GD();break;
case (0x22<<4)|2: _VDA(c->DBR);_SA((_GD()<<8)|c->AD);break;
case (0x22<<4)|3: _VDA(0);_SAD(_SP(_S(c)),c->PBR);_WR();break;
case (0x22<<4)|4: _SA(_SP(_S(c)--));c->AD=(_GD()<<8)|c->AD;break;
case (0x22<<4)|5: _VPA();_SA(c->PC++);break;
case (0x22<<4)|6: _VDA(0);c->PBR=_GD();_SAD(_SP(_S(c)--),c->PC>>8);_WR();break;
case (0x22<<4)|7: _VDA(0);_SAD(_SP(_S(c)--),c->PC);_WR();break;
case (0x22<<4)|8: c->PC=c->AD;_FETCH();break;
case (0x22<<4)|2: c->AD=(_GD()<<8)|c->AD;break;
case (0x22<<4)|3: _VDA(0);_SAD(_SP(_S(c)--),c->PBR);_WR();break;
case (0x22<<4)|4: _VPA();_SA(c->PC++);break;
case (0x22<<4)|5: _VDA(0);c->PBR=_GD();_SAD(_SP(_S(c)--),c->PC>>8);_WR();break;
case (0x22<<4)|6: _VDA(0);_SAD(_SP(_S(c)--),c->PC);_WR();break;
case (0x22<<4)|7: c->PC=c->AD;_FETCH();break;
case (0x22<<4)|8: assert(false);break;
/* AND d,s */
case (0x23<<4)|0: _VPA();_SA(c->PC++);break;
case (0x23<<4)|1: c->AD=_GD();break;
Expand Down
8 changes: 4 additions & 4 deletions src/codegen/w65c816s_gen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -730,11 +730,11 @@ def i_jsrx(o):
#-------------------------------------------------------------------------------
def i_jsl(o):
cmt(o,'JSL')
# replace last A_ABS tick - build 16-bit address from middle and low byte
o.to('c->AD=(_GD()<<8)|c->AD;')
# write Program Bank Register to stack
o.t('_VDA(0);_SAD(_SP(_S(c)),c->PBR);_WR();')
# put SP on addr bus, next cycle is a junk read
o.t('_SA(_SP(_S(c)--));c->AD=(_GD()<<8)|c->AD;')
# read bank of target address
o.t('_VDA(0);_SAD(_SP(_S(c)--),c->PBR);_WR();')
# read bank byte of target address
o.t('_VPA();_SA(c->PC++);')
# write PC high byte to stack
o.t('_VDA(0);c->PBR=_GD();_SAD(_SP(_S(c)--),c->PC>>8);_WR();')
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56 changes: 56 additions & 0 deletions src/tests/cputest.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -448,3 +448,59 @@ TEST_CASE("16 bit arithmetic carries") {
}
}
}

TEST_CASE("JSL instruction correctly sets PBR and PC") {
w65816_t cpu;
w65816_desc_t desc = {};
uint64_t pins = w65816_init(&cpu, &desc);

// skip RESET
pins &= ~(W65816_RW | W65816_RES);
cpu.PINS = pins;

// Test code: JSL $123456
// This tests that the middle byte ($34) is not lost
uint8_t asm_code[] = {
0x22, 0x56, 0x34, 0x12, // JSL $123456
};

// Memory for storing the code
uint8_t memory[0x10000] = {0};
memcpy(memory, asm_code, sizeof(asm_code));

// Set initial PC to 0x0000, PBR to 0x00
cpu.PC = 0x0000;
cpu.PBR = 0x00;
cpu.S = 0x01FF; // Stack pointer

int cycle = 0;

// Run for 8 cycles (JSL takes 8 cycles according to W65C816S datasheet)
while (cycle < 8) {
if (pins & W65816_RW) {
// memory read
// Get the full 24-bit address (bank:address)
uint32_t full_addr = W65816_GET_ADDR(pins);
uint8_t bank = (full_addr >> 16) & 0xFF;
uint16_t addr = full_addr & 0xFFFF;

// Read from our test memory
if (bank == 0 && addr < sizeof(memory)) {
W65816_SET_DATA(pins, memory[addr]);
} else {
W65816_SET_DATA(pins, 0xEA); // NOP
}
}

pins = w65816_tick(&cpu, pins);
cycle++;
}

// After JSL $123456, we expect:
// - PBR = 0x12
// - PC = 0x3456
CAPTURE(cpu.PBR);
CAPTURE(cpu.PC);
CHECK(cpu.PBR == 0x12);
CHECK(cpu.PC == 0x3456);
}
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