IDDR

The Input Double Data Rate (IDDR) primitive, also known as the DLPE, provides output data at the same clock edge in DDR mode. It has a logic diagram consisting of four D flip-flops (DFFN, DFF, DFF1, and DFF2), each with a similar structure. The input "D" is registered by each DFF, and the outputs "Q0", "Q1", etc., are provided to FPGA logic at the same clock edge.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
CLK	1	input
D	1	input
Q0	1	output
Q1	1	output

Parameters

Parameter	Default Value
Q0_INIT	0 (0b0)
Q1_INIT	0 (0b0)

Verilog Instantiation

IDDR #(
    .Q0_INIT(Q0_INIT),
    .Q1_INIT(Q1_INIT)
) iddr_inst (
    .CLK(CLK),
    .D(D),
    .Q0(Q0),
    .Q1(Q1)
);