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Pepijn de Vos edited this page Nov 19, 2024 · 2 revisions

OSER10

The OSER10 primitive is a 10-to-1 serializer that converts 10 bits of parallel data into 1 bit of serial output. It uses a primary clock (PCLK) which is typically obtained by dividing the high-speed clock (FCLK) frequency by 15, and it has inputs for the 10-bit parallel data, FCLK, PCLK, and an asynchronous reset signal. The primitive also has a single output, Q, which represents the serial output of the converted data.

This device is supported in Apicula.

Ports

Port Size Direction
D0 1 input
D1 1 input
D2 1 input
D3 1 input
D4 1 input
D5 1 input
D6 1 input
D7 1 input
D8 1 input
D9 1 input
FCLK 1 input
PCLK 1 input
Q 1 output
RESET 1 input

Parameters

Parameter Default Value
GSREN false
LSREN true

Verilog Instantiation

OSER10 #(
    .GSREN(GSREN),
    .LSREN(LSREN)
) oser10_inst (
    .D0(D0),
    .D1(D1),
    .D2(D2),
    .D3(D3),
    .D4(D4),
    .D5(D5),
    .D6(D6),
    .D7(D7),
    .D8(D8),
    .D9(D9),
    .FCLK(FCLK),
    .PCLK(PCLK),
    .Q(Q),
    .RESET(RESET)
);

OSER16

The OSER16 is a 16 to 1 serializer that converts 16 bits of parallel input into 1 bit of serial output. It typically uses an FCLK frequency divided by 18 to generate a PCLK, which drives the serialization process.

This device is supported in Apicula.

Ports

Port Size Direction
D0 1 input
D1 1 input
D10 1 input
D11 1 input
D12 1 input
D13 1 input
D14 1 input
D15 1 input
D2 1 input
D3 1 input
D4 1 input
D5 1 input
D6 1 input
D7 1 input
D8 1 input
D9 1 input
FCLK 1 input
PCLK 1 input
Q 1 output
RESET 1 input

Parameters

Parameter Default Value
GSREN false
LSREN true

Verilog Instantiation

OSER16 #(
    .GSREN(GSREN),
    .LSREN(LSREN)
) oser16_inst (
    .D0(D0),
    .D1(D1),
    .D10(D10),
    .D11(D11),
    .D12(D12),
    .D13(D13),
    .D14(D14),
    .D15(D15),
    .D2(D2),
    .D3(D3),
    .D4(D4),
    .D5(D5),
    .D6(D6),
    .D7(D7),
    .D8(D8),
    .D9(D9),
    .FCLK(FCLK),
    .PCLK(PCLK),
    .Q(Q),
    .RESET(RESET)
);

OSER4

The OSER4 primitive realizes a 4:1 parallel-to-serial conversion, with Q0 being the serial output. It also uses Q1 for the OEN signal of IOBUF/TBUF connected to Q0. The TX0/TX1 signal is used as the OEN input control signal of IOBUF/TBUF, and can be synchronized with data D0-D3 through DDR. When in TRI-DDRX2 mode, TX0/TX1 is output as Q1 connected to the OEN signal of IOBUF/TBUF, while in ODDRX2 mode, D0-D3 are output as Q0 connected to the data input I of IOBUF/TBUF in sequence (D0, D1, D2, D3).

This device is supported in Apicula.

Ports

Port Size Direction
D0 1 input
D1 1 input
D2 1 input
D3 1 input
FCLK 1 input
PCLK 1 input
Q0 1 output
Q1 1 output
RESET 1 input
TX0 1 input
TX1 1 input

Parameters

Parameter Default Value
GSREN false
HWL false
LSREN true
TXCLK_POL 0 (0b00000000000000000000000000000000)

Verilog Instantiation

OSER4 #(
    .GSREN(GSREN),
    .HWL(HWL),
    .LSREN(LSREN),
    .TXCLK_POL(TXCLK_POL)
) oser4_inst (
    .D0(D0),
    .D1(D1),
    .D2(D2),
    .D3(D3),
    .FCLK(FCLK),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .RESET(RESET),
    .TX0(TX0),
    .TX1(TX1)
);

OSER4_MEM

The OSER4_MEM primitive realizes 4:1 parallel serial conversion with memory, where the TCLK connects to the output signal DQSW0 or DQSW270 of DQS. It outputs data from the OSER4_MEM according to the TCLK clock edge, and Q0 is the serial output, while Q1 is used for the OEN signal of IOBUF/TBUF connected to Q0. The frequency relation among PCLK, FCLK, and TCLK is 2:1:1 (PCLK:FCLK:TCLK), and the phase relationship between FCLK and TCLK can be determined by the DLLSTEP and WSTEP values of DQS.

This device is not yet supported in Apicula

Ports

Port Size Direction
D0 1 input
D1 1 input
D2 1 input
D3 1 input
FCLK 1 input
PCLK 1 input
Q0 1 output
Q1 1 output
RESET 1 input
TCLK 1 input
TX0 1 input
TX1 1 input

Parameters

Parameter Default Value
GSREN
HWL
ID
LSREN
TCLK_SOURCE
TXCLK_POL

Verilog Instantiation

OSER4_MEM #(
    .GSREN(GSREN),
    .HWL(HWL),
    .ID(ID),
    .LSREN(LSREN),
    .TCLK_SOURCE(TCLK_SOURCE),
    .TXCLK_POL(TXCLK_POL)
) oser4_mem_inst (
    .D0(D0),
    .D1(D1),
    .D2(D2),
    .D3(D3),
    .FCLK(FCLK),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .RESET(RESET),
    .TCLK(TCLK),
    .TX0(TX0),
    .TX1(TX1)
);

OSER8

The 8-to-1 Serializer (OSER8) is a primitive that serializes 8 bits of parallel input into 1 bit of serial output. It has one output, Q0, which is the serial output, and one output, Q1, used as the OEN signal for an IOBUF/TBUF connected to Q0. The inputs are D0-D7, and it has clock inputs PCLK and FCLK, with RESET also available.

This device is supported in Apicula.

Ports

Port Size Direction
D0 1 input
D1 1 input
D2 1 input
D3 1 input
D4 1 input
D5 1 input
D6 1 input
D7 1 input
FCLK 1 input
PCLK 1 input
Q0 1 output
Q1 1 output
RESET 1 input
TX0 1 input
TX1 1 input
TX2 1 input
TX3 1 input

Parameters

Parameter Default Value
GSREN false
HWL false
LSREN true
TXCLK_POL 0 (0b00000000000000000000000000000000)

Verilog Instantiation

OSER8 #(
    .GSREN(GSREN),
    .HWL(HWL),
    .LSREN(LSREN),
    .TXCLK_POL(TXCLK_POL)
) oser8_inst (
    .D0(D0),
    .D1(D1),
    .D2(D2),
    .D3(D3),
    .D4(D4),
    .D5(D5),
    .D6(D6),
    .D7(D7),
    .FCLK(FCLK),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .RESET(RESET),
    .TX0(TX0),
    .TX1(TX1),
    .TX2(TX2),
    .TX3(TX3)
);

OSER8_MEM

The OSER8_MEM primitive realizes 8:1 parallel serial conversion, outputting data according to the TCLK clock edge. The Q0 signal is the serial output, and Q1 is used for the OEN signal of IOBUF/TBUF connected to Q0.

This device is not yet supported in Apicula

Ports

Port Size Direction
D0 1 input
D1 1 input
D2 1 input
D3 1 input
D4 1 input
D5 1 input
D6 1 input
D7 1 input
FCLK 1 input
PCLK 1 input
Q0 1 output
Q1 1 output
RESET 1 input
TCLK 1 input
TX0 1 input
TX1 1 input
TX2 1 input
TX3 1 input

Parameters

Parameter Default Value
HWL false
TCLK_SOURCE DQSW
TXCLK_POL 0 (0b0)

Verilog Instantiation

OSER8_MEM #(
    .HWL(HWL),
    .TCLK_SOURCE(TCLK_SOURCE),
    .TXCLK_POL(TXCLK_POL)
) oser8_mem_inst (
    .D0(D0),
    .D1(D1),
    .D2(D2),
    .D3(D3),
    .D4(D4),
    .D5(D5),
    .D6(D6),
    .D7(D7),
    .FCLK(FCLK),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .RESET(RESET),
    .TCLK(TCLK),
    .TX0(TX0),
    .TX1(TX1),
    .TX2(TX2),
    .TX3(TX3)
);
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