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MULT
Pepijn de Vos edited this page Nov 19, 2024
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The MULT12X12 primitive implements a 12-bit multiplier, which can perform multiplications: DOUT = A * B, DOUT = (A + D) * B, or DOUT = (A - D) * B. This operation is done using two multipliers within each DSP macro unit.
This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| A | 12 | input |
| B | 12 | input |
| CE | 2 | input |
| CLK | 2 | input |
| DOUT | 24 | output |
| RESET | 2 | input |
| Parameter | Default Value |
|---|---|
| AREG_CE | CE0 |
| AREG_CLK | BYPASS |
| AREG_RESET | RESET0 |
| BREG_CE | CE0 |
| BREG_CLK | BYPASS |
| BREG_RESET | RESET0 |
| MULT_RESET_MODE | SYNC |
| OREG_CE | CE0 |
| OREG_CLK | BYPASS |
| OREG_RESET | RESET0 |
| PREG_CE | CE0 |
| PREG_CLK | BYPASS |
| PREG_RESET | RESET0 |
MULT12X12 #(
.AREG_CE(AREG_CE),
.AREG_CLK(AREG_CLK),
.AREG_RESET(AREG_RESET),
.BREG_CE(BREG_CE),
.BREG_CLK(BREG_CLK),
.BREG_RESET(BREG_RESET),
.MULT_RESET_MODE(MULT_RESET_MODE),
.OREG_CE(OREG_CE),
.OREG_CLK(OREG_CLK),
.OREG_RESET(OREG_RESET),
.PREG_CE(PREG_CE),
.PREG_CLK(PREG_CLK),
.PREG_RESET(PREG_RESET)
) mult12x12_inst (
.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.DOUT(DOUT),
.RESET(RESET)
);The Gowin MULT18X18 primitive supports 18-bit multiplication, taking two 18-bit inputs A and B, and producing a 36-bit output. It has multiple control ports for data selection, enable, clocking, and reset, indicating its potential to be used in more complex digital signal processing applications.
This device is supported in Apicula
| Port | Size | Direction |
|---|---|---|
| A | 18 | input |
| ASEL | 1 | input |
| ASIGN | 1 | input |
| B | 18 | input |
| BSEL | 1 | input |
| BSIGN | 1 | input |
| CE | 1 | input |
| CLK | 1 | input |
| DOUT | 36 | output |
| RESET | 1 | input |
| SIA | 18 | input |
| SIB | 18 | input |
| SOA | 18 | output |
| SOB | 18 | output |
| Parameter | Default Value |
|---|---|
| AREG | 0 (0b0) |
| ASIGN_REG | 0 (0b0) |
| BREG | 0 (0b0) |
| BSIGN_REG | 0 (0b0) |
| MULT_RESET_MODE | SYNC |
| OUT_REG | 0 (0b0) |
| PIPE_REG | 0 (0b0) |
| SOA_REG | 0 (0b0) |
MULT18X18 #(
.AREG(AREG),
.ASIGN_REG(ASIGN_REG),
.BREG(BREG),
.BSIGN_REG(BSIGN_REG),
.MULT_RESET_MODE(MULT_RESET_MODE),
.OUT_REG(OUT_REG),
.PIPE_REG(PIPE_REG),
.SOA_REG(SOA_REG)
) mult18x18_inst (
.A(A),
.ASEL(ASEL),
.ASIGN(ASIGN),
.B(B),
.BSEL(BSEL),
.BSIGN(BSIGN),
.CE(CE),
.CLK(CLK),
.DOUT(DOUT),
.RESET(RESET),
.SIA(SIA),
.SIB(SIB),
.SOA(SOA),
.SOB(SOB)
);The MULT27X36 primitive implements 27-bit x 36-bit multiplication. It takes two inputs, A[26:0] and B[35:0], and produces a 62-bit output DOUT[62:0]. The input values are stored in registers, and the operation is controlled by clock (CLK), enable (CE), and reset (RESET) signals.
This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| A | 27 | input |
| B | 36 | input |
| CE | 2 | input |
| CLK | 2 | input |
| D | 26 | input |
| DOUT | 63 | output |
| PADDSUB | 1 | input |
| PSEL | 1 | input |
| RESET | 2 | input |
| Parameter | Default Value |
|---|---|
| AREG_CE | CE0 |
| AREG_CLK | BYPASS |
| AREG_RESET | RESET0 |
| BREG_CE | CE0 |
| BREG_CLK | BYPASS |
| BREG_RESET | RESET0 |
| DREG_CE | CE0 |
| DREG_CLK | BYPASS |
| DREG_RESET | RESET0 |
| DYN_P_ADDSUB | FALSE |
| DYN_P_SEL | FALSE |
| MULT_RESET_MODE | SYNC |
| OREG_CE | CE0 |
| OREG_CLK | BYPASS |
| OREG_RESET | RESET0 |
| PADDSUB_IREG_CE | CE0 |
| PADDSUB_IREG_CLK | BYPASS |
| PADDSUB_IREG_RESET | RESET0 |
| PREG_CE | CE0 |
| PREG_CLK | BYPASS |
| PREG_RESET | RESET0 |
| PSEL_IREG_CE | CE0 |
| PSEL_IREG_CLK | BYPASS |
| PSEL_IREG_RESET | RESET0 |
| P_ADDSUB | 0 (0b0) |
| P_SEL | 0 (0b0) |
MULT27X36 #(
.AREG_CE(AREG_CE),
.AREG_CLK(AREG_CLK),
.AREG_RESET(AREG_RESET),
.BREG_CE(BREG_CE),
.BREG_CLK(BREG_CLK),
.BREG_RESET(BREG_RESET),
.DREG_CE(DREG_CE),
.DREG_CLK(DREG_CLK),
.DREG_RESET(DREG_RESET),
.DYN_P_ADDSUB(DYN_P_ADDSUB),
.DYN_P_SEL(DYN_P_SEL),
.MULT_RESET_MODE(MULT_RESET_MODE),
.OREG_CE(OREG_CE),
.OREG_CLK(OREG_CLK),
.OREG_RESET(OREG_RESET),
.PADDSUB_IREG_CE(PADDSUB_IREG_CE),
.PADDSUB_IREG_CLK(PADDSUB_IREG_CLK),
.PADDSUB_IREG_RESET(PADDSUB_IREG_RESET),
.PREG_CE(PREG_CE),
.PREG_CLK(PREG_CLK),
.PREG_RESET(PREG_RESET),
.PSEL_IREG_CE(PSEL_IREG_CE),
.PSEL_IREG_CLK(PSEL_IREG_CLK),
.PSEL_IREG_RESET(PSEL_IREG_RESET),
.P_ADDSUB(P_ADDSUB),
.P_SEL(P_SEL)
) mult27x36_inst (
.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.D(D),
.DOUT(DOUT),
.PADDSUB(PADDSUB),
.PSEL(PSEL),
.RESET(RESET)
);The MULT36X36 primitive supports 36-bit multiplication, as indicated by its name. It takes two 36-bit inputs A and B, and produces a 72-bit output MOUT[71:0]. The inputs are denoted as REGA (or IREGA) for A and REGB (or IREGB) for B, while the output is DOUT. The primitive also includes control signals such as CLK, CE, RESET, ASIGN, and BSIGN.
This device is supported in Apicula.
| Port | Size | Direction |
|---|---|---|
| A | 36 | input |
| ASIGN | 1 | input |
| B | 36 | input |
| BSIGN | 1 | input |
| CE | 1 | input |
| CLK | 1 | input |
| DOUT | 72 | output |
| RESET | 1 | input |
| Parameter | Default Value |
|---|---|
| AREG | 0 (0b0) |
| ASIGN_REG | 0 (0b0) |
| BREG | 0 (0b0) |
| BSIGN_REG | 0 (0b0) |
| MULT_RESET_MODE | SYNC |
| OUT0_REG | 0 (0b0) |
| OUT1_REG | 0 (0b0) |
| PIPE_REG | 0 (0b0) |
MULT36X36 #(
.AREG(AREG),
.ASIGN_REG(ASIGN_REG),
.BREG(BREG),
.BSIGN_REG(BSIGN_REG),
.MULT_RESET_MODE(MULT_RESET_MODE),
.OUT0_REG(OUT0_REG),
.OUT1_REG(OUT1_REG),
.PIPE_REG(PIPE_REG)
) mult36x36_inst (
.A(A),
.ASIGN(ASIGN),
.B(B),
.BSIGN(BSIGN),
.CE(CE),
.CLK(CLK),
.DOUT(DOUT),
.RESET(RESET)
);The Gowin MULT9X9 primitive supports 9-bit multiplication, implementing the mathematical operation: DOUT = A * B.
This device is supported in Apicula.
| Port | Size | Direction |
|---|---|---|
| A | 9 | input |
| ASEL | 1 | input |
| ASIGN | 1 | input |
| B | 9 | input |
| BSEL | 1 | input |
| BSIGN | 1 | input |
| CE | 1 | input |
| CLK | 1 | input |
| DOUT | 18 | output |
| RESET | 1 | input |
| SIA | 9 | input |
| SIB | 9 | input |
| SOA | 9 | output |
| SOB | 9 | output |
| Parameter | Default Value |
|---|---|
| AREG | 0 (0b0) |
| ASIGN_REG | 0 (0b0) |
| BREG | 0 (0b0) |
| BSIGN_REG | 0 (0b0) |
| MULT_RESET_MODE | SYNC |
| OUT_REG | 0 (0b0) |
| PIPE_REG | 0 (0b0) |
| SOA_REG | 0 (0b0) |
MULT9X9 #(
.AREG(AREG),
.ASIGN_REG(ASIGN_REG),
.BREG(BREG),
.BSIGN_REG(BSIGN_REG),
.MULT_RESET_MODE(MULT_RESET_MODE),
.OUT_REG(OUT_REG),
.PIPE_REG(PIPE_REG),
.SOA_REG(SOA_REG)
) mult9x9_inst (
.A(A),
.ASEL(ASEL),
.ASIGN(ASIGN),
.B(B),
.BSEL(BSEL),
.BSIGN(BSIGN),
.CE(CE),
.CLK(CLK),
.DOUT(DOUT),
.RESET(RESET),
.SIA(SIA),
.SIB(SIB),
.SOA(SOA),
.SOB(SOB)
);This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| CASI | 24 | input |
| CASO | 24 | output |
| CE | 1 | input |
| CLK | 1 | input |
| COFFIN0 | 6 | input |
| COFFIN1 | 6 | input |
| COFFIN2 | 6 | input |
| DATAIN0 | 10 | input |
| DATAIN1 | 10 | input |
| DATAIN2 | 10 | input |
| DATAO | 24 | output |
| RSTN | 1 | input |
| Parameter | Default Value |
|---|---|
| ACC_EN | FALSE |
| CASI_EN | FALSE |
| CASO_EN | FALSE |
| COFFIN_WIDTH | 4 (0b00000000000000000000000000000100) |
| DATAIN_WIDTH | 8 (0b00000000000000000000000000001000) |
| IREG | 0 (0b0) |
| OREG | 0 (0b0) |
| PREG | 0 (0b0) |
MULTACC #(
.ACC_EN(ACC_EN),
.CASI_EN(CASI_EN),
.CASO_EN(CASO_EN),
.COFFIN_WIDTH(COFFIN_WIDTH),
.DATAIN_WIDTH(DATAIN_WIDTH),
.IREG(IREG),
.OREG(OREG),
.PREG(PREG)
) multacc_inst (
.CASI(CASI),
.CASO(CASO),
.CE(CE),
.CLK(CLK),
.COFFIN0(COFFIN0),
.COFFIN1(COFFIN1),
.COFFIN2(COFFIN2),
.DATAIN0(DATAIN0),
.DATAIN1(DATAIN1),
.DATAIN2(DATAIN2),
.DATAO(DATAO),
.RSTN(RSTN)
);The MULTADDALU12x12 primitive implements a 48-bit ALU operation, followed by two 12 x 12 multiplier outputs. It has four operation modes, including: (1) DOUBT = A0 * B0 ± A1 * B1, (2) DOUBT = DOUBT ± (A0 * B0 ± A1 * B1), (3) DOUBT = CASI ± A0 * B0 ± A1 * B1, and (4) DOUBT = CASI ± (A0 * B0 ± A1 * B1) + DOUBT.
This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| A0 | 12 | input |
| A1 | 12 | input |
| ACCSEL | 1 | input |
| ADDSUB | 2 | input |
| B0 | 12 | input |
| B1 | 12 | input |
| CASI | 48 | input |
| CASISEL | 1 | input |
| CASO | 48 | output |
| CE | 2 | input |
| CLK | 2 | input |
| DOUT | 48 | output |
| RESET | 2 | input |
| Parameter | Default Value |
|---|---|
| A0REG_CE | CE0 |
| A0REG_CLK | BYPASS |
| A0REG_RESET | RESET0 |
| A1REG_CE | CE0 |
| A1REG_CLK | BYPASS |
| A1REG_RESET | RESET0 |
| ACCSEL_IREG_CE | CE0 |
| ACCSEL_IREG_CLK | BYPASS |
| ACCSEL_IREG_RESET | RESET0 |
| ACCSEL_PREG_CE | CE0 |
| ACCSEL_PREG_CLK | BYPASS |
| ACCSEL_PREG_RESET | RESET0 |
| ACC_SEL | 0 (0b0) |
| ADDSUB0_IREG_CE | CE0 |
| ADDSUB0_IREG_CLK | BYPASS |
| ADDSUB0_IREG_RESET | RESET0 |
| ADDSUB0_PREG_CE | CE0 |
| ADDSUB0_PREG_CLK | BYPASS |
| ADDSUB0_PREG_RESET | RESET0 |
| ADDSUB1_IREG_CE | CE0 |
| ADDSUB1_IREG_CLK | BYPASS |
| ADDSUB1_IREG_RESET | RESET0 |
| ADDSUB1_PREG_CE | CE0 |
| ADDSUB1_PREG_CLK | BYPASS |
| ADDSUB1_PREG_RESET | RESET0 |
| ADD_SUB_0 | 0 (0b0) |
| ADD_SUB_1 | 0 (0b0) |
| B0REG_CE | CE0 |
| B0REG_CLK | BYPASS |
| B0REG_RESET | RESET0 |
| B1REG_CE | CE0 |
| B1REG_CLK | BYPASS |
| B1REG_RESET | RESET0 |
| CASISEL_IREG_CE | CE0 |
| CASISEL_IREG_CLK | BYPASS |
| CASISEL_IREG_RESET | RESET0 |
| CASISEL_PREG_CE | CE0 |
| CASISEL_PREG_CLK | BYPASS |
| CASISEL_PREG_RESET | RESET0 |
| CASI_SEL | 0 (0b0) |
| DYN_ACC_SEL | FALSE |
| DYN_ADD_SUB_0 | FALSE |
| DYN_ADD_SUB_1 | FALSE |
| DYN_CASI_SEL | FALSE |
| FB_PREG_EN | FALSE |
| MULT_RESET_MODE | SYNC |
| OREG_CE | CE0 |
| OREG_CLK | BYPASS |
| OREG_RESET | RESET0 |
| PREG0_CE | CE0 |
| PREG0_CLK | BYPASS |
| PREG0_RESET | RESET0 |
| PREG1_CE | CE0 |
| PREG1_CLK | BYPASS |
| PREG1_RESET | RESET0 |
| PRE_LOAD | 0 (0b000000000000000000000000000000000000000000000000) |
MULTADDALU12X12 #(
.A0REG_CE(A0REG_CE),
.A0REG_CLK(A0REG_CLK),
.A0REG_RESET(A0REG_RESET),
.A1REG_CE(A1REG_CE),
.A1REG_CLK(A1REG_CLK),
.A1REG_RESET(A1REG_RESET),
.ACCSEL_IREG_CE(ACCSEL_IREG_CE),
.ACCSEL_IREG_CLK(ACCSEL_IREG_CLK),
.ACCSEL_IREG_RESET(ACCSEL_IREG_RESET),
.ACCSEL_PREG_CE(ACCSEL_PREG_CE),
.ACCSEL_PREG_CLK(ACCSEL_PREG_CLK),
.ACCSEL_PREG_RESET(ACCSEL_PREG_RESET),
.ACC_SEL(ACC_SEL),
.ADDSUB0_IREG_CE(ADDSUB0_IREG_CE),
.ADDSUB0_IREG_CLK(ADDSUB0_IREG_CLK),
.ADDSUB0_IREG_RESET(ADDSUB0_IREG_RESET),
.ADDSUB0_PREG_CE(ADDSUB0_PREG_CE),
.ADDSUB0_PREG_CLK(ADDSUB0_PREG_CLK),
.ADDSUB0_PREG_RESET(ADDSUB0_PREG_RESET),
.ADDSUB1_IREG_CE(ADDSUB1_IREG_CE),
.ADDSUB1_IREG_CLK(ADDSUB1_IREG_CLK),
.ADDSUB1_IREG_RESET(ADDSUB1_IREG_RESET),
.ADDSUB1_PREG_CE(ADDSUB1_PREG_CE),
.ADDSUB1_PREG_CLK(ADDSUB1_PREG_CLK),
.ADDSUB1_PREG_RESET(ADDSUB1_PREG_RESET),
.ADD_SUB_0(ADD_SUB_0),
.ADD_SUB_1(ADD_SUB_1),
.B0REG_CE(B0REG_CE),
.B0REG_CLK(B0REG_CLK),
.B0REG_RESET(B0REG_RESET),
.B1REG_CE(B1REG_CE),
.B1REG_CLK(B1REG_CLK),
.B1REG_RESET(B1REG_RESET),
.CASISEL_IREG_CE(CASISEL_IREG_CE),
.CASISEL_IREG_CLK(CASISEL_IREG_CLK),
.CASISEL_IREG_RESET(CASISEL_IREG_RESET),
.CASISEL_PREG_CE(CASISEL_PREG_CE),
.CASISEL_PREG_CLK(CASISEL_PREG_CLK),
.CASISEL_PREG_RESET(CASISEL_PREG_RESET),
.CASI_SEL(CASI_SEL),
.DYN_ACC_SEL(DYN_ACC_SEL),
.DYN_ADD_SUB_0(DYN_ADD_SUB_0),
.DYN_ADD_SUB_1(DYN_ADD_SUB_1),
.DYN_CASI_SEL(DYN_CASI_SEL),
.FB_PREG_EN(FB_PREG_EN),
.MULT_RESET_MODE(MULT_RESET_MODE),
.OREG_CE(OREG_CE),
.OREG_CLK(OREG_CLK),
.OREG_RESET(OREG_RESET),
.PREG0_CE(PREG0_CE),
.PREG0_CLK(PREG0_CLK),
.PREG0_RESET(PREG0_RESET),
.PREG1_CE(PREG1_CE),
.PREG1_CLK(PREG1_CLK),
.PREG1_RESET(PREG1_RESET),
.PRE_LOAD(PRE_LOAD)
) multaddalu12x12_inst (
.A0(A0),
.A1(A1),
.ACCSEL(ACCSEL),
.ADDSUB(ADDSUB),
.B0(B0),
.B1(B1),
.CASI(CASI),
.CASISEL(CASISEL),
.CASO(CASO),
.CE(CE),
.CLK(CLK),
.DOUT(DOUT),
.RESET(RESET)
);This device is supported in Apicula.
| Port | Size | Direction |
|---|---|---|
| A0 | 18 | input |
| A1 | 18 | input |
| ACCLOAD | 1 | input |
| ASEL | 2 | input |
| ASIGN | 2 | input |
| B0 | 18 | input |
| B1 | 18 | input |
| BSEL | 2 | input |
| BSIGN | 2 | input |
| C | 54 | input |
| CASI | 55 | input |
| CASO | 55 | output |
| CE | 1 | input |
| CLK | 1 | input |
| DOUT | 54 | output |
| RESET | 1 | input |
| SIA | 18 | input |
| SIB | 18 | input |
| SOA | 18 | output |
| SOB | 18 | output |
| Parameter | Default Value |
|---|---|
| A0REG | 0 (0b0) |
| A1REG | 0 (0b0) |
| ACCLOAD_REG0 | 0 (0b0) |
| ACCLOAD_REG1 | 0 (0b0) |
| ASIGN0_REG | 0 (0b0) |
| ASIGN1_REG | 0 (0b0) |
| B0REG | 0 (0b0) |
| B1REG | 0 (0b0) |
| BSIGN0_REG | 0 (0b0) |
| BSIGN1_REG | 0 (0b0) |
| B_ADD_SUB | 0 (0b0) |
| CREG | 0 (0b0) |
| C_ADD_SUB | 0 (0b0) |
| MULTADDALU18X18_MODE | 0 (0b00000000000000000000000000000000) |
| MULT_RESET_MODE | SYNC |
| OUT_REG | 0 (0b0) |
| PIPE0_REG | 0 (0b0) |
| PIPE1_REG | 0 (0b0) |
| SOA_REG | 0 (0b0) |
MULTADDALU18X18 #(
.A0REG(A0REG),
.A1REG(A1REG),
.ACCLOAD_REG0(ACCLOAD_REG0),
.ACCLOAD_REG1(ACCLOAD_REG1),
.ASIGN0_REG(ASIGN0_REG),
.ASIGN1_REG(ASIGN1_REG),
.B0REG(B0REG),
.B1REG(B1REG),
.BSIGN0_REG(BSIGN0_REG),
.BSIGN1_REG(BSIGN1_REG),
.B_ADD_SUB(B_ADD_SUB),
.CREG(CREG),
.C_ADD_SUB(C_ADD_SUB),
.MULTADDALU18X18_MODE(MULTADDALU18X18_MODE),
.MULT_RESET_MODE(MULT_RESET_MODE),
.OUT_REG(OUT_REG),
.PIPE0_REG(PIPE0_REG),
.PIPE1_REG(PIPE1_REG),
.SOA_REG(SOA_REG)
) multaddalu18x18_inst (
.A0(A0),
.A1(A1),
.ACCLOAD(ACCLOAD),
.ASEL(ASEL),
.ASIGN(ASIGN),
.B0(B0),
.B1(B1),
.BSEL(BSEL),
.BSIGN(BSIGN),
.C(C),
.CASI(CASI),
.CASO(CASO),
.CE(CE),
.CLK(CLK),
.DOUT(DOUT),
.RESET(RESET),
.SIA(SIA),
.SIB(SIB),
.SOA(SOA),
.SOB(SOB)
);The MULTALU18X18 primitive is a 36x18 multiplier with ALU function that supports three arithmetic modes: addition, subtraction, and multiply. The operation performed by the primitive can be selected from these three options based on the values of the C_ADD_SUB input.
This device is supported in Apicula.
| Port | Size | Direction |
|---|---|---|
| A | 18 | input |
| ACCLOAD | 1 | input |
| ASIGN | 1 | input |
| B | 18 | input |
| BSIGN | 1 | input |
| C | 54 | input |
| CASI | 55 | input |
| CASO | 55 | output |
| CE | 1 | input |
| CLK | 1 | input |
| D | 54 | input |
| DOUT | 54 | output |
| DSIGN | 1 | input |
| RESET | 1 | input |
| Parameter | Default Value |
|---|---|
| ACCLOAD_REG0 | 0 (0b0) |
| ACCLOAD_REG1 | 0 (0b0) |
| AREG | 0 (0b0) |
| ASIGN_REG | 0 (0b0) |
| BREG | 0 (0b0) |
| BSIGN_REG | 0 (0b0) |
| B_ADD_SUB | 0 (0b0) |
| CREG | 0 (0b0) |
| C_ADD_SUB | 0 (0b0) |
| DREG | 0 (0b0) |
| DSIGN_REG | 0 (0b0) |
| MULTALU18X18_MODE | 0 (0b00000000000000000000000000000000) |
| MULT_RESET_MODE | SYNC |
| OUT_REG | 0 (0b0) |
| PIPE_REG | 0 (0b0) |
MULTALU18X18 #(
.ACCLOAD_REG0(ACCLOAD_REG0),
.ACCLOAD_REG1(ACCLOAD_REG1),
.AREG(AREG),
.ASIGN_REG(ASIGN_REG),
.BREG(BREG),
.BSIGN_REG(BSIGN_REG),
.B_ADD_SUB(B_ADD_SUB),
.CREG(CREG),
.C_ADD_SUB(C_ADD_SUB),
.DREG(DREG),
.DSIGN_REG(DSIGN_REG),
.MULTALU18X18_MODE(MULTALU18X18_MODE),
.MULT_RESET_MODE(MULT_RESET_MODE),
.OUT_REG(OUT_REG),
.PIPE_REG(PIPE_REG)
) multalu18x18_inst (
.A(A),
.ACCLOAD(ACCLOAD),
.ASIGN(ASIGN),
.B(B),
.BSIGN(BSIGN),
.C(C),
.CASI(CASI),
.CASO(CASO),
.CE(CE),
.CLK(CLK),
.D(D),
.DOUT(DOUT),
.DSIGN(DSIGN),
.RESET(RESET)
);The MULTALU27X18 (27x18 Multiplier with ALU) implements multiplication, multiply-add, accumulation, multiply-accumulate, shift based on multiplication/multiply-add/accumulation/multiply-accumulate, cascade based on multiplication/multiply-add/accumulation/multiply-accumulate, pre-addition and pre-subtraction based on multiplication/multiply-add/accumulation/multiply-accumulate.
This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| A | 27 | input |
| ACCSEL | 1 | input |
| ADDSUB | 2 | input |
| ASEL | 1 | input |
| B | 18 | input |
| C | 48 | input |
| CASI | 48 | input |
| CASISEL | 1 | input |
| CASO | 48 | output |
| CE | 2 | input |
| CLK | 2 | input |
| CSEL | 1 | input |
| D | 26 | input |
| DOUT | 48 | output |
| PADDSUB | 1 | input |
| PSEL | 1 | input |
| RESET | 2 | input |
| SIA | 27 | input |
| SOA | 27 | output |
| Parameter | Default Value |
|---|---|
| ACCSEL_IREG_CE | CE0 |
| ACCSEL_IREG_CLK | BYPASS |
| ACCSEL_IREG_RESET | RESET0 |
| ACCSEL_PREG_CE | CE0 |
| ACCSEL_PREG_CLK | BYPASS |
| ACCSEL_PREG_RESET | RESET0 |
| ACC_SEL | 0 (0b0) |
| ADDSUB0_IREG_CE | CE0 |
| ADDSUB0_IREG_CLK | BYPASS |
| ADDSUB0_IREG_RESET | RESET0 |
| ADDSUB0_PREG_CE | CE0 |
| ADDSUB0_PREG_CLK | BYPASS |
| ADDSUB0_PREG_RESET | RESET0 |
| ADDSUB1_IREG_CE | CE0 |
| ADDSUB1_IREG_CLK | BYPASS |
| ADDSUB1_IREG_RESET | RESET0 |
| ADDSUB1_PREG_CE | CE0 |
| ADDSUB1_PREG_CLK | BYPASS |
| ADDSUB1_PREG_RESET | RESET0 |
| ADD_SUB_0 | 0 (0b0) |
| ADD_SUB_1 | 0 (0b0) |
| AREG_CE | CE0 |
| AREG_CLK | BYPASS |
| AREG_RESET | RESET0 |
| A_SEL | 0 (0b0) |
| BREG_CE | CE0 |
| BREG_CLK | BYPASS |
| BREG_RESET | RESET0 |
| CASISEL_IREG_CE | CE0 |
| CASISEL_IREG_CLK | BYPASS |
| CASISEL_IREG_RESET | RESET0 |
| CASISEL_PREG_CE | CE0 |
| CASISEL_PREG_CLK | BYPASS |
| CASISEL_PREG_RESET | RESET0 |
| CASI_SEL | 0 (0b0) |
| CSEL_IREG_CE | CE0 |
| CSEL_IREG_CLK | BYPASS |
| CSEL_IREG_RESET | RESET0 |
| CSEL_PREG_CE | CE0 |
| CSEL_PREG_CLK | BYPASS |
| CSEL_PREG_RESET | RESET0 |
| C_IREG_CE | CE0 |
| C_IREG_CLK | BYPASS |
| C_IREG_RESET | RESET0 |
| C_PREG_CE | CE0 |
| C_PREG_CLK | BYPASS |
| C_PREG_RESET | RESET0 |
| C_SEL | 1 (0b1) |
| DREG_CE | CE0 |
| DREG_CLK | BYPASS |
| DREG_RESET | RESET0 |
| DYN_ACC_SEL | FALSE |
| DYN_ADD_SUB_0 | FALSE |
| DYN_ADD_SUB_1 | FALSE |
| DYN_A_SEL | FALSE |
| DYN_CASI_SEL | FALSE |
| DYN_C_SEL | FALSE |
| DYN_P_ADDSUB | FALSE |
| DYN_P_SEL | FALSE |
| FB_PREG_EN | FALSE |
| MULT12X12_EN | FALSE |
| MULT_RESET_MODE | SYNC |
| OREG_CE | CE0 |
| OREG_CLK | BYPASS |
| OREG_RESET | RESET0 |
| PADDSUB_IREG_CE | CE0 |
| PADDSUB_IREG_CLK | BYPASS |
| PADDSUB_IREG_RESET | RESET0 |
| PREG_CE | CE0 |
| PREG_CLK | BYPASS |
| PREG_RESET | RESET0 |
| PRE_LOAD | 0 (0b000000000000000000000000000000000000000000000000) |
| PSEL_IREG_CE | CE0 |
| PSEL_IREG_CLK | BYPASS |
| PSEL_IREG_RESET | RESET0 |
| P_ADDSUB | 0 (0b0) |
| P_SEL | 0 (0b0) |
| SOA_PREG_EN | FALSE |
MULTALU27X18 #(
.ACCSEL_IREG_CE(ACCSEL_IREG_CE),
.ACCSEL_IREG_CLK(ACCSEL_IREG_CLK),
.ACCSEL_IREG_RESET(ACCSEL_IREG_RESET),
.ACCSEL_PREG_CE(ACCSEL_PREG_CE),
.ACCSEL_PREG_CLK(ACCSEL_PREG_CLK),
.ACCSEL_PREG_RESET(ACCSEL_PREG_RESET),
.ACC_SEL(ACC_SEL),
.ADDSUB0_IREG_CE(ADDSUB0_IREG_CE),
.ADDSUB0_IREG_CLK(ADDSUB0_IREG_CLK),
.ADDSUB0_IREG_RESET(ADDSUB0_IREG_RESET),
.ADDSUB0_PREG_CE(ADDSUB0_PREG_CE),
.ADDSUB0_PREG_CLK(ADDSUB0_PREG_CLK),
.ADDSUB0_PREG_RESET(ADDSUB0_PREG_RESET),
.ADDSUB1_IREG_CE(ADDSUB1_IREG_CE),
.ADDSUB1_IREG_CLK(ADDSUB1_IREG_CLK),
.ADDSUB1_IREG_RESET(ADDSUB1_IREG_RESET),
.ADDSUB1_PREG_CE(ADDSUB1_PREG_CE),
.ADDSUB1_PREG_CLK(ADDSUB1_PREG_CLK),
.ADDSUB1_PREG_RESET(ADDSUB1_PREG_RESET),
.ADD_SUB_0(ADD_SUB_0),
.ADD_SUB_1(ADD_SUB_1),
.AREG_CE(AREG_CE),
.AREG_CLK(AREG_CLK),
.AREG_RESET(AREG_RESET),
.A_SEL(A_SEL),
.BREG_CE(BREG_CE),
.BREG_CLK(BREG_CLK),
.BREG_RESET(BREG_RESET),
.CASISEL_IREG_CE(CASISEL_IREG_CE),
.CASISEL_IREG_CLK(CASISEL_IREG_CLK),
.CASISEL_IREG_RESET(CASISEL_IREG_RESET),
.CASISEL_PREG_CE(CASISEL_PREG_CE),
.CASISEL_PREG_CLK(CASISEL_PREG_CLK),
.CASISEL_PREG_RESET(CASISEL_PREG_RESET),
.CASI_SEL(CASI_SEL),
.CSEL_IREG_CE(CSEL_IREG_CE),
.CSEL_IREG_CLK(CSEL_IREG_CLK),
.CSEL_IREG_RESET(CSEL_IREG_RESET),
.CSEL_PREG_CE(CSEL_PREG_CE),
.CSEL_PREG_CLK(CSEL_PREG_CLK),
.CSEL_PREG_RESET(CSEL_PREG_RESET),
.C_IREG_CE(C_IREG_CE),
.C_IREG_CLK(C_IREG_CLK),
.C_IREG_RESET(C_IREG_RESET),
.C_PREG_CE(C_PREG_CE),
.C_PREG_CLK(C_PREG_CLK),
.C_PREG_RESET(C_PREG_RESET),
.C_SEL(C_SEL),
.DREG_CE(DREG_CE),
.DREG_CLK(DREG_CLK),
.DREG_RESET(DREG_RESET),
.DYN_ACC_SEL(DYN_ACC_SEL),
.DYN_ADD_SUB_0(DYN_ADD_SUB_0),
.DYN_ADD_SUB_1(DYN_ADD_SUB_1),
.DYN_A_SEL(DYN_A_SEL),
.DYN_CASI_SEL(DYN_CASI_SEL),
.DYN_C_SEL(DYN_C_SEL),
.DYN_P_ADDSUB(DYN_P_ADDSUB),
.DYN_P_SEL(DYN_P_SEL),
.FB_PREG_EN(FB_PREG_EN),
.MULT12X12_EN(MULT12X12_EN),
.MULT_RESET_MODE(MULT_RESET_MODE),
.OREG_CE(OREG_CE),
.OREG_CLK(OREG_CLK),
.OREG_RESET(OREG_RESET),
.PADDSUB_IREG_CE(PADDSUB_IREG_CE),
.PADDSUB_IREG_CLK(PADDSUB_IREG_CLK),
.PADDSUB_IREG_RESET(PADDSUB_IREG_RESET),
.PREG_CE(PREG_CE),
.PREG_CLK(PREG_CLK),
.PREG_RESET(PREG_RESET),
.PRE_LOAD(PRE_LOAD),
.PSEL_IREG_CE(PSEL_IREG_CE),
.PSEL_IREG_CLK(PSEL_IREG_CLK),
.PSEL_IREG_RESET(PSEL_IREG_RESET),
.P_ADDSUB(P_ADDSUB),
.P_SEL(P_SEL),
.SOA_PREG_EN(SOA_PREG_EN)
) multalu27x18_inst (
.A(A),
.ACCSEL(ACCSEL),
.ADDSUB(ADDSUB),
.ASEL(ASEL),
.B(B),
.C(C),
.CASI(CASI),
.CASISEL(CASISEL),
.CASO(CASO),
.CE(CE),
.CLK(CLK),
.CSEL(CSEL),
.D(D),
.DOUT(DOUT),
.PADDSUB(PADDSUB),
.PSEL(PSEL),
.RESET(RESET),
.SIA(SIA),
.SOA(SOA)
);The MULTALU36X18 supports three arithmetic modes: *DOUT A B C (two's complement), *DOUT A B (addition), and *DOUT A B CASI (CASI mode, details not specified).
This device is supported in Apicula.
| Port | Size | Direction |
|---|---|---|
| A | 18 | input |
| ACCLOAD | 1 | input |
| ASIGN | 1 | input |
| B | 36 | input |
| BSIGN | 1 | input |
| C | 54 | input |
| CASI | 55 | input |
| CASO | 55 | output |
| CE | 1 | input |
| CLK | 1 | input |
| DOUT | 54 | output |
| RESET | 1 | input |
| Parameter | Default Value |
|---|---|
| ACCLOAD_REG0 | 0 (0b0) |
| ACCLOAD_REG1 | 0 (0b0) |
| AREG | 0 (0b0) |
| ASIGN_REG | 0 (0b0) |
| BREG | 0 (0b0) |
| BSIGN_REG | 0 (0b0) |
| CREG | 0 (0b0) |
| C_ADD_SUB | 0 (0b0) |
| MULTALU36X18_MODE | 0 (0b00000000000000000000000000000000) |
| MULT_RESET_MODE | SYNC |
| OUT_REG | 0 (0b0) |
| PIPE_REG | 0 (0b0) |
MULTALU36X18 #(
.ACCLOAD_REG0(ACCLOAD_REG0),
.ACCLOAD_REG1(ACCLOAD_REG1),
.AREG(AREG),
.ASIGN_REG(ASIGN_REG),
.BREG(BREG),
.BSIGN_REG(BSIGN_REG),
.CREG(CREG),
.C_ADD_SUB(C_ADD_SUB),
.MULTALU36X18_MODE(MULTALU36X18_MODE),
.MULT_RESET_MODE(MULT_RESET_MODE),
.OUT_REG(OUT_REG),
.PIPE_REG(PIPE_REG)
) multalu36x18_inst (
.A(A),
.ACCLOAD(ACCLOAD),
.ASIGN(ASIGN),
.B(B),
.BSIGN(BSIGN),
.C(C),
.CASI(CASI),
.CASO(CASO),
.CE(CE),
.CLK(CLK),
.DOUT(DOUT),
.RESET(RESET)
);