ODDR

The ODDR (ODDR) primitive, also known as Dual Data Rate Output, is used for transferring double data rate signals from FPGA devices. The Q0 output is the double rate data output, while Q1 is used for the OEN signal of an IOBUF/TBUF connected by Q1.

This device is supported in Apicula.

Ports

Port	Size	Direction
CLK	1	input
D0	1	input
D1	1	input
Q0	1	output
Q1	1	output
TX	1	input

Parameters

Parameter	Default Value
INIT	0 (0b00000000000000000000000000000000)
TXCLK_POL	0 (0b00000000000000000000000000000000)

Verilog Instantiation

ODDR #(
    .INIT(INIT),
    .TXCLK_POL(TXCLK_POL)
) oddr_inst (
    .CLK(CLK),
    .D0(D0),
    .D1(D1),
    .Q0(Q0),
    .Q1(Q1),
    .TX(TX)
);