OSIDES32

OSIDES32

Ports

Port	Size	Direction
D	1	input
DF0	1	output
DF1	1	output
DLYSTEP0	8	input
DLYSTEP1	8	input
FCLKN	1	input
FCLKP	1	input
FCLKQN	1	input
FCLKQP	1	input
PCLK	1	input
Q	32	output
RESET	1	input
SDTAP0	1	input
SDTAP1	1	input
VALUE0	1	input
VALUE1	1	input

Parameters

Parameter	Default Value
ADAPT_EN_0	FALSE
ADAPT_EN_1	FALSE
C_STATIC_DLY_0	0 (0b00000000000000000000000000000000)
C_STATIC_DLY_1	0 (0b00000000000000000000000000000000)
DYN_DLY_EN_0	FALSE
DYN_DLY_EN_1	FALSE

Verilog Instantiation

OSIDES32 #(
    .ADAPT_EN_0(ADAPT_EN_0),
    .ADAPT_EN_1(ADAPT_EN_1),
    .C_STATIC_DLY_0(C_STATIC_DLY_0),
    .C_STATIC_DLY_1(C_STATIC_DLY_1),
    .DYN_DLY_EN_0(DYN_DLY_EN_0),
    .DYN_DLY_EN_1(DYN_DLY_EN_1)
) osides32_inst (
    .D(D),
    .DF0(DF0),
    .DF1(DF1),
    .DLYSTEP0(DLYSTEP0),
    .DLYSTEP1(DLYSTEP1),
    .FCLKN(FCLKN),
    .FCLKP(FCLKP),
    .FCLKQN(FCLKQN),
    .FCLKQP(FCLKQP),
    .PCLK(PCLK),
    .Q(Q),
    .RESET(RESET),
    .SDTAP0(SDTAP0),
    .SDTAP1(SDTAP1),
    .VALUE0(VALUE0),
    .VALUE1(VALUE1)
);