OSIDES32

The OSIDES32 primitive is a deserializer that takes 1 bit serial input and produces 32 bits parallel output, implementing an oversampling serial-to-parallel function. It can be achieved using two Input/Output Latches (IOLs) with asynchronous reset support, but does not have the capability to adjust the output data sequence using CALIB. The oversampling process involves four FCLK phases, P, QP, N, and QN, which are 0°, 90°, 180°, and 270° respectively, and are related to the primary clock (PCLK) by a frequency relationship of fPCLK = 1/4fFCLKP.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
D	1	input
DF0	1	output
DF1	1	output
DLYSTEP0	8	input
DLYSTEP1	8	input
FCLKN	1	input
FCLKP	1	input
FCLKQN	1	input
FCLKQP	1	input
PCLK	1	input
Q	32	output
RESET	1	input
SDTAP0	1	input
SDTAP1	1	input
VALUE0	1	input
VALUE1	1	input

Parameters

Parameter	Default Value
ADAPT_EN_0	FALSE
ADAPT_EN_1	FALSE
C_STATIC_DLY_0	0 (0b00000000000000000000000000000000)
C_STATIC_DLY_1	0 (0b00000000000000000000000000000000)
DYN_DLY_EN_0	FALSE
DYN_DLY_EN_1	FALSE

Verilog Instantiation

OSIDES32 #(
    .ADAPT_EN_0(ADAPT_EN_0),
    .ADAPT_EN_1(ADAPT_EN_1),
    .C_STATIC_DLY_0(C_STATIC_DLY_0),
    .C_STATIC_DLY_1(C_STATIC_DLY_1),
    .DYN_DLY_EN_0(DYN_DLY_EN_0),
    .DYN_DLY_EN_1(DYN_DLY_EN_1)
) osides32_inst (
    .D(D),
    .DF0(DF0),
    .DF1(DF1),
    .DLYSTEP0(DLYSTEP0),
    .DLYSTEP1(DLYSTEP1),
    .FCLKN(FCLKN),
    .FCLKP(FCLKP),
    .FCLKQN(FCLKQN),
    .FCLKQP(FCLKQP),
    .PCLK(PCLK),
    .Q(Q),
    .RESET(RESET),
    .SDTAP0(SDTAP0),
    .SDTAP1(SDTAP1),
    .VALUE0(VALUE0),
    .VALUE1(VALUE1)
);