PADD18

The Gowin PADD18 primitive performs the function of pre-add, pre-subtract, or shifting with an 18-bit input. It takes two 18-bit inputs A and B, a 1-bit control signal +/-, and produces an 18-bit output DOUT. The primitive also has registers to enhance timing functionality.

This device is supported in Apicula.

Ports

Port	Size	Direction
A	18	input
ASEL	1	input
B	18	input
CE	1	input
CLK	1	input
DOUT	18	output
RESET	1	input
SBI	18	input
SBO	18	output
SI	18	input
SO	18	output

Parameters

Parameter	Default Value
ADD_SUB	0 (0b0)
AREG	0 (0b0)
BREG	0 (0b0)
BSEL_MODE	1 (0b1)
PADD_RESET_MODE	SYNC
SOREG	0 (0b0)

Verilog Instantiation

PADD18 #(
    .ADD_SUB(ADD_SUB),
    .AREG(AREG),
    .BREG(BREG),
    .BSEL_MODE(BSEL_MODE),
    .PADD_RESET_MODE(PADD_RESET_MODE),
    .SOREG(SOREG)
) padd18_inst (
    .A(A),
    .ASEL(ASEL),
    .B(B),
    .CE(CE),
    .CLK(CLK),
    .DOUT(DOUT),
    .RESET(RESET),
    .SBI(SBI),
    .SBO(SBO),
    .SI(SI),
    .SO(SO)
);