Add parsing of verilog module port renaming (aliases) #5478
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xiota
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xiota
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No "larger effort". Basically rebased from #3339.
Motivation: @thotypous told me, "that patch is quite important. Without it, yosys cannot synthesize output from the bluespec compiler."
@jix said of the earlier PR, "The overall approach looks good." But apparently didn't merge because:
I tried to add detection for edge cases, but was unable to without breaking intended behavior. If important, someone else would need to do it later.
Fixes #2613
Fixes #3334