riscv_opcode_dref

RISC-V: Add INSN_DREF to memory read/write instructions

• Branch: riscv-opcode-dref
• Tracking PR: #90 (view Pull Request and Diff)
• Mailing List:
  • PATCH v1 (2022-11-18)

Conflicts With

• Cleaning: Opcode Tidying (Batch 1)
  It also touches definition of some T-Head custom instructions.

Feature Description

This commit adds INSN_DREF flag (and size-related flags) to instruction which reads/writes the memory directly. It however excludes cache-related instructions that does synchronization with other cores but otherwise does not touch the contents of the memory.

INSN_DREF and size flags are added to following instructions:

• cbo.zero
• All instructions from following custom extensions:
  • XTheadFMemIdx
  • XTheadInt
  • XTheadMemIdx
  • XTheadMemPair

References

• T-Head ISA extension specification (Xthead*)
  version 2.1.0, 2022-11-07.