India RISC-V Chip Tapeout Programm

RTL2GDS_vsdflow

Week0 - Tools Installation

---

1. Yosys Installation

$ git clone https://github.com/YosysHQ/yosys.git
$ cd yosys 
$ sudo apt install make (If make is not installed please install it) 
$ sudo apt-get install build-essential clang bison flex \
    libreadline-dev gawk tcl-dev libffi-dev git \
    graphviz xdot pkg-config python3 libboost-system-dev \
    libboost-python-dev libboost-filesystem-dev zlib1g-dev
$ make 
$ sudo make install

✅ Yosys Successfully Installed

---

---

2. Iverilog

$ sudo apt-get install iverilog

✅ Iverilog Successfully Installed

---

---

3. GTKWave

$ sudo apt update
$ sudo apt install gtkwave

✅ GTKWave Successfully Installed

---

---

4. Ngspice

$ sudo apt update
$ sudo apt install ngspice

✅ Ngspice Successfully Installed

---

---

5. Magic vlsi

# Install required dependencies
sudo apt-get install m4
sudo apt-get install tcsh
sudo apt-get install csh
sudo apt-get install libx11-dev
sudo apt-get install tcl-dev tk-dev
sudo apt-get install libcairo2-dev
sudo apt-get install mesa-common-dev libglu1-mesa-dev
sudo apt-get install libncurses-dev

# Clone Magic repository
git clone https://github.com/RTimothyEdwards/magic
cd magic

# Configure build
./configure

# Build Magic
make

# Install system-wide
sudo make install

✅ Magic VLSI Successfully Installed

---

Week1

RTL design and synthesis

Netlist for Yosys

---

iverilog & gtkwave implimentation example 2x1 mux o/p wave

---

Week2

Overview

The VSDBabySoC is a simple SoC (System-on-Chip) design incorporating a RISC-V processor (rvmyth), a PLL (Phase-Locked Loop) module (pll), and a DAC (Digital-to-Analog Converter) module (dac). This project demonstrates integration of these IP cores and aims to simulate and verify the design behavior using pre-synthesis and post-synthesis simulations.

Project Structure

• src/include/ - Contains header files (*.vh) with necessary macros or parameter definitions.
• src/module/ - Contains Verilog files for each module in the SoC design.
• output/ - Directory where compiled outputs and simulation files will be generated.

Requirements

Ensure you have Icarus Verilog installed for compilation and GTKWave for viewing waveform files. This project assumes a Unix-like environment (macOS/Linux).

Step-by-Step Guide

1. Setup and Prepare Project Directory

Clone or set up the directory structure as follows:

VSDBabySoC/
├── src/
│   ├── include/
│   │   ├── sandpiper.vh
│   │   └── other header files...
│   ├── module/
│   │   ├── vsdbabysoc.v      # Top-level module integrating all components
│   │   ├── rvmyth.v          # RISC-V core module
│   │   ├── avsdpll.v         # PLL module
│   │   ├── avsddac.v         # DAC module
│   │   └── testbench.v       # Testbench for simulation
└── output/
└── compiled_tlv/         # Holds compiled intermediate files if needed

Module Descriptions

2.1 vsdbabysoc.v (Top-Level SoC Module)

This is the top-level module that integrates the rvmyth, pll, and dac modules.
[VSDBabySoC](https://github.com/manili/VSDBabySoC.git)

  - Inputs:
     - reset: Resets the core processor.
     - VCO_IN, ENb_CP, ENb_VCO, REF: PLL control signals.
     - VREFH: DAC reference voltage.
  - Outputs:
     - OUT: Analog output from DAC.
     - Connections:
     - RV_TO_DAC - A 10-bit bus that connects the RISC-V core output to the DAC input.
     - CLK - The clock signal generated by the PLL.

2.2 rvmyth.v (RISC-V Core)

The rvmyth module is a simple RISC-V based processor. It outputs a 10-bit digital signal (OUT) to be converted by the DAC.
[rvmyth](https://github.com/kunalg123/rvmyth/)

  Inputs:
     - CLK: Clock signal generated by the PLL.
     - reset: Initializes or resets the processor.
  Outputs:
     - OUT: A 10-bit digital signal representing processed data to be sent to the DAC.

2.3 avsdpll.v (PLL Module)

The pll module is a phase-locked loop that generates a stable clock (CLK) for the RISC-V core.
[Introduction](https://github.com/ireneann713/PLL.git) [avsdpll](https://github.com/lakshmi-sathi/avsdpll_1v8.git)

  Inputs:
     - VCO_IN, ENb_CP, ENb_VCO, REF: Control and reference signals for PLL operation.
  Output:
     - CLK: A stable clock signal for synchronizing the core and other modules.

2.4 avsddac.v (DAC Module)

The dac module converts the 10-bit digital signal from the rvmyth core to an analog output.
[avsddac](https://github.com/vsdip/rvmyth_avsddac_interface.git)

  Inputs:
     - D: A 10-bit digital input from the processor.
     - VREFH: Reference voltage for the DAC.
  Output:
     - OUT: Analog output signal.

Testbench

The testbench.v file is a test module to verify the functionality of vsdbabysoc. It includes signal initialization, clock generation, and waveform dumping for both pre-synthesis and post-synthesis simulations. Waveform Output:

• pre_synth_sim.vcd or post_synth_sim.vcd files generated based on simulation conditions.

Simulation Steps

Pre-Synthesis Simulation

Run the following command to perform a pre-synthesis simulation:

iverilog -o output/pre_synth_sim/pre_synth_sim.out -DPRE_SYNTH_SIM \
    -I src/include -I src/module \
    src/module/testbench.v src/module/vsdbabysoc.v
cd output/pre_synth_sim
./pre_synth_sim.out

Explanation:

• -DPRE_SYNTH_SIM: Defines the PRE_SYNTH_SIM macro for conditional compilation in the testbench.
• The resulting pre_synth_sim.vcd file can be viewed in GTKWave.

Viewing Waveform in GTKWave

After running the simulation, open the VCD file in GTKWave: gtkwave output/pre_synth_sim/pre_synth_sim.vcd

Post-Synthesis Simulation

To run a post-synthesis simulation, use:

iverilog -o output/post_synth_sim/post_synth_sim.out -DPOST_SYNTH_SIM \
    -I src/include -I src/module \
    src/module/testbench.v output/synthesized/vsdbabysoc.synth.v
cd output/post_synth_sim
./post_synth_sim.out

Trouble shooting tips

• Module Redefinition: If you encounter redefinition errors, ensure modules are included only once, either in the testbench or in the command line.
• Path Issues: Verify paths specified with -I are correct. Use full paths if relative paths cause errors.

Yosys final report

Week3

GLS OF BABYSOC

POST-SYNTHESIS SIMULATION

Purpose of GLS:

Gate-Level Simulation is used to verify the functionality of a design after the synthesis process. Unlike behavioral or RTL (Register Transfer Level) simulations, which are performed at a higher level of abstraction, GLS works on the netlist generated post-synthesis. This netlist includes the actual gates and connections used to implement the design.

Key Aspects of GLS for BabySoC:

1. Verification with Timing Information:

   • GLS is performed using Standard Delay Format (SDF) files to ensure timing correctness.
   • This checks if the SoC behaves as expected under real-world timing constraints.

2. Design Validation Post-Synthesis:

   • Confirms that the design's logical behavior remains correct after mapping it to the gate-level representation.
   • Ensures that the design is free from issues like metastability or glitches.

3. Simulation Tools:

   • Tools like Icarus Verilog or a similar simulator can be used for compiling and running the gate-level netlist.
   • Waveforms are typically analyzed using GTKWave.

4. Importance for BabySoC:

   • BabySoC consists of multiple modules like the RISC-V processor, PLL, and DAC. GLS ensures that these modules interact correctly and meet the timing requirements in the synthesized design.

Here is the step-by-step execution plan for running the commands manually:

Step 1: Load the Top-Level Design and Supporting Modules

yosys

Inside the Yosys shell, run:

read_verilog /home/aadarsh/VSDBabySoC/src/module/vsdbabysoc.v
read_verilog -I /home/aadarsh/VSDBabySoC/src/include /home/ananya123/VSDBabySoCC/src/module/rvmyth.v
read_verilog -I /home/aadarsh/VSDBabySoC/src/include /home/ananya123/VSDBabySoCC/src/module/clk_gate.v

Step 2: Load the Liberty Files for Synthesis

Inside the same Yosys shell, run:

read_liberty -lib /home/aadarsh/VSDBabySoC/src/lib/avsdpll.lib
read_liberty -lib /home/aadarsh/VSDBabySoC/src/lib/avsddac.lib
read_liberty -lib /home/aadarsh/VSDBabySoC/src/lib/sky130_fd_sc_hd__tt_025C_1v80.lib

---

Step 3: Run Synthesis Targeting vsdbabysoc

synth -top vsdbabysoc

---

Step 4: Map D Flip-Flops to Standard Cells

dfflibmap -liberty /home/aadarsh/VSDBabySoC/src/lib/sky130_fd_sc_hd__tt_025C_1v80.lib

---

Step 5: Perform Optimization and Technology Mapping

opt

---

Step 6: Check Statistics

stat

---

Step 7: Write the Synthesized Netlist

write_verilog -noattr /home/aadarsh/VSDBabySoC/output/post_synth_sim/vsdbabysoc.synth.v

---

Week4

---

Details

In MOSFET device characterization, multiple experiments are conducted to understand its electrical behavior under different operating conditions. Each experiment provides insight into specific physical parameters and performance characteristics that are crucial for circuit design.

---

1️⃣ Id vs Vds (Output Characteristics)

This experiment measures the drain current (Id) as a function of the drain-to-source voltage (Vds) for different gate-to-source voltages (Vgs). ✅ Purpose:

To analyze the MOSFET’s behavior in linear (ohmic) and saturation regions.

To determine the transition between regions.

To calculate parameters like output resistance (ro) and channel modulation (λ).

---

2️⃣ Id vs Vgs (Transfer Characteristics)

This experiment plots drain current (Id) versus gate-to-source voltage (Vgs) at a fixed Vds. ✅ Purpose:

To determine threshold voltage (Vth).

To understand the device’s transconductance (gm) and gate control over the channel.

To analyze how Id increases with gate bias in saturation.

---

3️⃣ VTC (Voltage Transfer Characteristics) of CMOS Inverter

In this test, the output voltage (Vout) of a CMOS inverter is measured against varying input voltage (Vin). ✅ Purpose:

To analyze the switching behavior of the inverter.

To find noise margins (NMH, NML).

To determine the inverter threshold voltage (Vm).

To evaluate the logic gain and switching region sharpness.

---

4️⃣ Transconductance Evaluation (gm vs Vgs or gm vs Id)

This involves extracting gm as Vgs or Id is varied. ✅ Purpose:

To evaluate how efficiently the MOSFET converts gate voltage variations into drain current.

To optimize the device for analog circuit applications like amplifiers.

---

5️⃣ Subthreshold Region (Id vs Vgs in Log Scale)

This is performed at low Vgs values with logarithmic Id scaling. ✅ Purpose:

To analyze MOSFET behavior in weak inversion.

To extract subthreshold slope (SS) and understand leakage currents, important for low-power design.

---

6️⃣ Capacitance Measurements (Cgs, Cgd vs Vgs)

Capacitances are measured as Vgs is varied. ✅ Purpose:

To evaluate charging/discharging time in digital circuits.

To analyze delay, speed, and AC performance.

---

---

---

noise margin

---

power supply variation

---

Device variation