Staging/xlnx/2026r1/ad9088 backports#3211
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nunojsa merged 84 commits intoxlnx/release/linux-v6.12.y-2026r1from Mar 26, 2026
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Staging/xlnx/2026r1/ad9088 backports#3211nunojsa merged 84 commits intoxlnx/release/linux-v6.12.y-2026r1from
nunojsa merged 84 commits intoxlnx/release/linux-v6.12.y-2026r1from
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CiprianRegus,
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buha,
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Mar 26, 2026
Add proper VCO and PFD limits for versal based platforms. For that we need to add new Technology and Speed grade defines. tbd: upstream this patch Signed-off-by: Nuno Sá <nuno.sa@analog.com>
Make sure that we can validate the schema and DT example. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
Make sure that we can validate the schema and DT example. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Document common properties of the JESD FSM framework. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
This adds support for reading 204C lane latency. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
This patch adds support for external synchronization in the AXI ADC driver. It introduces detection of external sync capability via the ADI_EXT_SYNC bit in the configuration register. A new sysfs interface is added to control synchronization: - sync_start_enable: allows triggering sync actions (arm, disarm, trigger_manual) depending on hardware capabilities. - sync_start_enable_available: lists available sync actions. These additions enable more flexible synchronization control for multi-device setups and JESD204-based systems. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
The ADI support for the driver will include a HDL IP which will support 8-bit transfers as well as a different data load address from the base address. To differentiate from the original driver a ID system has been added and changes have been made based on the ID. Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
The HDL IP can be configured to run in 8, 16 and 32 bit mode. This will extend the capabilities of the current driver to support 16 bit implementations using compatibility strings. Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
The HDL IP can be configured to run in 8, 16 and 32 bit mode. This will extend the capabilities of the current driver to support 32 bit implementations using compatibility strings. Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
In case of LTC6952 we need a REFin can VCOin. Assuming VCOin is provided by CCF, add support for setting the desired rate. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
CPMID should be cleared after init. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
…ings Add round_rate callback, which seem to be needed. Set required mode bits for integer and fractional mode automatically. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
When a DMA transfer is done, the vchan_cookie_complete triggers the axi_dmac_desc_free which is called in IRQ context. This triggers the BUG_ON in vunmap function. To solve this issue a workqueue is created to schedule axi_dmac_desc_free to be performed outside of interrupt context. Signed-off-by: Eliza Balas <eliza.balas@analog.com>
The maximum BSYNC output frequency is 200 MHz per the datasheet, not 250 MHz. The previous value of 250 MHz corresponds to the REFIN maximum, not the BSYNC output maximum. Fixes: 54bbd40 ("iio: frequency: support the adf4030 Synchronizer") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
The datasheet requires resetting the TDC_ERR monitor (set then clear RST_TDC_ERR in Register 0x61 bit 7) before starting a TDC measurement. Without this step, stale error flags from a previous measurement could persist. Fixes: 54bbd40 ("iio: frequency: support the adf4030 Synchronizer") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
The ADF4030 reports die temperature in sign-magnitude format: Register 0x92 holds the 8-bit magnitude in degrees C and Register 0x93 bit 0 holds the sign (0=positive, 1=negative). The driver was incorrectly using sign_extend32() which assumes two's complement encoding, producing wrong results for negative temperatures. Fixes: 54bbd40 ("iio: frequency: support the adf4030 Synchronizer") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Add configuration for AD9084 Versal based projects. Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com> Signed-off-by: Nuno Sá <nuno.sa@analog.com>
Add default config for microblaze apollo builds. While at it, add a small update on the base microblaze defconfig. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
A command-line utility for inspecting and validating AD9088 calibration data files. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Nuno Sá <nuno.sa@analog.com>
ad9088_cal_dump is a tool that's not normally compiled. Hence ignore it for our relevant ci builds. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
…0.1.3 Added: - API - Added support for AD9088 - API - Support for a new Profile format that consolidates and improves the data structures used by the part - this is a breaking change for Profile versions prior to V10. See Components Section below for Profile version - API - Integrated support for external trigger-based frequency hopping - API - New function to read part number with X-grade or B-grade and SW trim information (SW Trim 1/3/5) - FW - Allow ADC/DAC PN signal inversion based on user Profile settings Changed: - API - Some code cleanup and optimization by deleting unused code - API - Converted frequency representations from Hz to uHz (microhertz) throughout the ADF4030 driver and example code - this is a breaking change - FW - Upgrade device Profile. See Components Section below for Profile version - FW - For SerDes Rx, a number of bridging cal settings come from device Profile - FW - Device clock frequency variable changed from kHz to Hz - FW - Define the P-N inversion of the differential ADC/DAC RFIO in the device Profile - FW - 4D slice mode switching optimization - FW - Optimized receiver handling of overrange signal conditions Deprecated: - API - adi_apollo_clk_mcs_internal_sysref_per_set(), sync_logic_reset(), adi_apollo_jrx_subclass_set(), adi_apollo_clk_mcs_trig_reset_serdes_enable(), adi_apollo_adc_tlines_offset_set(), hsci_regio_rmw_write32() Fixed: - API - Bug fixed in adi_apollo_tmode_config_set(). Previously, the function ignored the resolution parameter and always set 16-bit resolution - API - Bug fixed in adi_apollo_cnco_profile_load() whereby an incorrect value could be written to the Profile when less than a full Profile array was being loaded - API - Bug fixed in tx_txpath_misc_configure() whereby register values were not updated - API - Increased delay after freezing of ADC background calibration before executing ADC slice mode switch within the slice mode switch prepare API function - FW - Bug fixed whereby MCS side-B was not being updated correctly during tracking calibration with dual clocking Errata: - API - ADF4030-FPGA Time-of-Flight measurement may time out when operating at low BSYNC frequencies - API - AD9084-SE ADC performance has not been fully optimized Supported: - AD9088 - AD9084 Components: - Device Driver API 2.0.10 - Firmware 2.0.6 - Device Profile 10.1.28 Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 92e2dca)
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit aa086cb)
…SREF divider Add adi,subclass = <1> to all four TRX nodes and compute LTC6953_AION_BSYNC_6_DIVIDER dynamically from FREQ_J1_MHz / SYSREF_CLK_MHz. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit c65095b)
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 432e559)
ad9088_gpio_setup() returned -EINVAL when the adi,gpio-exports property was not present in the device tree, preventing probe on boards that don't need GPIO exports. Return 0 instead since the property is optional. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit ee9e664)
…amping Update ADF4382_PHASE_BLEED_CNST_DIV from 285 to 250 and replace the simple 8-bit mask with proper bounds checking and clamping for the phase adjust register value. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 459ebbf)
… to u32 Add debugfs read/write support for mcs_track_decimation allowing runtime adjustment of the MCS tracking calibration TDC decimation rate. Change mcs_track_decimation from u16 to u32 to match the API. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 35f7883)
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 1efa496)
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit c9c919f)
Align the debugfs MCS tracking calibration path with the JESD204 FSM implementation: - Move ADF4382 auto-align enable and phase adjustment (125) into ad9088_mcs_tracking_cal_setup() so both FSM and debugfs paths configure the ADF4382 before foreground tracking runs - Remove the now-duplicate ADF4382 setup from the JESD204 FSM post_setup_stage1 handler - Add adi_apollo_mcs_cal_tracking_enable(device, 0) to the debugfs bg_track_cal_run teardown path (write 0), matching the FSM teardown which calls both abort and tracking_enable(0) Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 7e0fc48)
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 9a9655c)
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit d225de8)
Remove the FIXME workaround that patched profiles with version patch < 3 by modifying reserved_cfg fields and forcing sysref_present. This is no longer needed now that all profiles have been updated to v10.1.3+. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 29c2257)
…ia DT When the device tree overrides the JESD subclass to a non-zero value (subclass 1), ensure that at least one SYSREF input is marked as present. If neither side A nor side B SYSREF is already configured in the profile, enable the center SYSREF so that deterministic latency synchronization can function correctly. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 2ea51df)
ADC slice mode read/write and the adc_mode_switch_enable_set call during setup are not supported in 8T8R profiles. Guard these paths with is_8t8r checks to avoid errors on 8T8R configurations. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit d86b74b)
…le array OOB
Fix several 8T8R channel mapping bugs in the IIO channel-to-hardware
block mapping function:
1. TX/RX FDUC/FDDC logical-to-physical conversion: The xbar encoding
interleaves bands per channel (TXn*4 + BAND*2 + Q), but the mux
hardware uses physical numbering where all BAND0 come first (0-3)
then BAND1 (4-7). Convert using lookup table {0,4,1,5,2,6,3,7}.
Without this, TX fine NCOs target wrong hardware blocks and RX
channels only see a subset of CDDCs/ADCs.
2. TX mux0_sel lookup: mux0_sel[] is indexed by DAC number with the
value selecting a mod-switch output, not indexed by CDUC. For 8T8R,
the modsw mapping swaps CDUCs 1/2. Search mux0_sel[] for the
matching modsw output to find the correct DAC.
3. RX mux0_out_adc_sel indexing: The array is indexed by CB_OUT number,
not CDDC number. Add cddc_to_cbout[] translation for 8T8R.
4. Profile array OOB: tx_cduc[]/rx_cddc[] have 2 entries per side but
8T8R hardware CDUC/CDDC numbers go 0-3. Similarly tx_fduc[]/rx_fddc[]
have 4 entries but physical numbers go 0-7. Add fddc_pi/cddc_pi
profile index fields to chan_map, computed once with modular indexing
(% CDUCS_PER_SIDE, % FDUCS_PER_SIDE). This fixes the "Invalid
adi_apollo_cduc_ratio_e enum" error on channels 2-3.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
(cherry picked from commit efac716)
The CFIR data path switch only handled FDDC masks for 4T4R (A0-A3, B0-B3). For 8T8R, FDDCs 4-7 share the same CFIR instances as 0-3 but use data paths DP_2 and DP_3 instead of DP_0/DP_1. Without this, probing an 8T8R profile logs "Unhandled FDDC number" errors for all upper-band FDDCs. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 90cc759)
In 8T8R mode, BMEM pairs share SRAM: A0/A2, A1/A3, B0/B2, B1/B3 all map to the same physical SRAM addresses. When both channels of a pair are captured, the hardware interleaves their data — even words belong to the primary channel, odd words to the secondary. Without this fix, both channels in a shared pair read identical raw data from the same SRAM address, producing duplicate waveforms. Fix by: 1. Doubling the SRAM capture range (end_addr) for 8T8R to account for the interleaving overhead — each channel only gets every other word. 2. After reading, deinterleave in-place: extract even words into the primary channel's buffer and odd words into the secondary's, then halve word_count for the demux loop. The in-place deinterleave is safe because the destination index is always less than the source index (dst[i] from src[2*i]). Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 41f3be1)
Setting spi_txen_en and spi_rxen_en to !!val caused the hardware to fall back to pin control mode when disabling (val=0), because spi_txen_en=0 means "use TxEN/RxEN pin" rather than "disable via SPI". This made disable operations unreliable, depending on the physical pin state. Fix by always setting spi_txen_en and spi_rxen_en to 1 to remain in SPI control mode, and use spi_txen/spi_rxen to control the actual enable state. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 0046a1c)
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 9aa1804)
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit 79ee390)
…d DTS variants Add DTS files for VCU118 quad AD9084 RevB external primary and second board configurations, for both default and 26.4 GHz lane rate profiles. These override the adf4030 node and configure JESD204 FSM stop states. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> (cherry picked from commit ef06bf0)
Suppress frame-larger-than and enum-conversion for some files in the AD9088 API. Ideally we would fix the BU APIs and get those fixes "upstream". Signed-off-by: Jorge Marques <jorge.marques@analog.com> (cherry picked from commit 09ac6b7)
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PR Description
This cleanly cherry-picked the following PRs:
#3179
#3181
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