Staging/xlnx/2026r1/ad9088 backports

Documentation/devicetree/bindings/iio/adc/adi,ad9083.yaml

@@ -15,6 +15,9 @@ description: |
   here:
     https://www.analog.com/media/en/technical-documentation/data-sheets/ad9083.pdf
 
+allOf:
+  - $ref: /schemas/jesd204/jesd204-device-props.yaml#
+
 properties:
   compatible:
     enum:
@@ -23,24 +26,17 @@ properties:
   reg:
     maxItems: 1
 
-  jesd204-device:
-    description: Device is added to the jesd204-fsm framework
-    type: boolean
-
   '#jesd204-cells':
     const: 2
 
   jesd204-top-device:
-    $ref: /schemas/types.yaml#/definitions/uint32
     const: 0
 
   jesd204-link-ids:
-    $ref: /schemas/types.yaml#/definitions/uint32
-    const: 0
+    items:
+      - const: 0
 
   jesd204-inputs:
-    description: JESD204-fsm devices phandles and specifiers (used to build the link topology)
-    $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
   spi-max-frequency:
@@ -185,7 +181,7 @@ required:
   - clocks
   - clock-names
 
-additionalProperties: false
+unevaluatedProperties: false
 
 examples:
   - |
@@ -198,6 +194,7 @@ examples:
       adc0_ad9083: ad9083@0 {
         compatible = "adi,ad9083";
         reg = <0>;
+
         jesd204-device;
         #jesd204-cells = <2>;
         jesd204-top-device = <0>;

Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml

@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/frequency/adi,adf4382.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADF4382 Microwave Wideband Synthesizer with Integrated VCO
+
+maintainers:
+  - Antoniu Miclaus <antoniu.miclaus@analog.com>
+  - Ciprian Hegbeli <ciprian.hegbeli@analog.com>
+
+description: The ADF4382 is a high performance, ultralow jitter, Frac-N PLL with
+   integrated VCO ideally suited for LO generation for 5G applications
+   or data converter clock applications.
+
+   https://www.analog.com/en/products/adf4382a.html
+
+properties:
+  compatible:
+    enum:
+      - adi,adf4382
+      - adi,adf4382a
+
+  reg:
+    maxItems: 1
+
+  spi-max-frequency:
+    maximum: 75000000
+
+  clocks:
+    description: Clock to provide CLKIN reference clock signal.
+    maxItems: 1
+
+  clock-names:
+    description:
+      External clock that provides reference input frequency.
+    items:
+      - const: ref_clk
+
+  '#clock-cells':
+    const: 0
+
+  clock-output-names:
+    maxItems: 1
+
+  adi,charge-pump-microamp:
+    description:
+      The charge pump current that the external loop filter was designed for.
+      If this property is not specified, then the charge pump current is set to the
+      default 11100uA. The valid values are listed below. However, if the set value is
+      not supported, the driver will look for the closest valid charge pump current.
+    enum: [790, 990, 1190, 1380, 1590, 1980, 2390, 2790, 3180, 3970, 4770, 5570, 6330, 7910, 9510, 11100]
+
+  adi,ref-divider:
+    description:
+      Input divider of the reference frequency, cannot be lower then 1 or
+      higher then 63.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 1
+    maximum: 63
+    default: 1
+
+
+  adi,ref-doubler-enable:
+    description:
+      Enables the doubling of the reference clock.
+    type: boolean
+
+  adi,bleed-word:
+    description:
+      A small programmable constant charge pump current, known as bleed current,
+      can be used to optimize the phase noise and fractional spurious signals
+      in fractional mode.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 4095
+    default: 0
+
+  adi,power-up-frequency:
+    description:
+      PLL tunes to the set frequency on probe or defaults to 2,305 GHz.
+    $ref: /schemas/types.yaml#/definitions/uint64
+    minimum: 687500000
+    maximum: 22000000000
+    default: 2305000000
+
+  adi,output-power-value:
+    description:
+      The output power amplitude level which will be applied for both channels
+      at startup.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 15
+    default: 11
+
+  adi,spi-3wire-enable:
+    description:
+      Uses SPI in 3 wire mode, by default is uses 4 wire mode.
+    type: boolean
+
+  adi,cmos-3v3:
+    description:
+      Sets the SPI logic to 3.3V, by defautl it uses 1,8V.
+    type: boolean
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        frequency@0 {
+            compatible = "adi,adf4382";
+            reg = <0>;
+            spi-max-frequency = <1000000>;
+            clocks = <&adf4382_clkin>;
+            clock-names = "ref_clk";
+            adi,charge-pump-microamp = <2390>;
+            adi,ref-divider = <1>;
+        };
+    };
+...

Documentation/devicetree/bindings/iio/multiplexer/iio-gen-mux.yaml

@@ -2,10 +2,10 @@
 # Copyright 2021 Analog Devices Inc.
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/iio/multiplexer/io-gen-mux.yaml#
+$id: http://devicetree.org/schemas/iio/multiplexer/iio-gen-mux.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: I/O generic multiplexer bindings
+title: I/O generic multiplexer
 
 maintainers:
   - Michael Hennerich <michael.hennerich@analog.com>
@@ -21,9 +21,8 @@ description: |
   is described in Documentation/devicetree/bindings/mux/mux-controller.yaml
 
 properties:
-
   compatible:
-    const: io-channel-mux
+    const: adi,gen_mux
 
   mux-controls: true
 
@@ -57,23 +56,22 @@ examples:
   - |
     #include <dt-bindings/gpio/gpio.h>
 
-    mux0: mux-controller {
-      compatible = "gpio-mux";
-      #mux-control-cells = <0>;
+    mux: mux-controller {
+        compatible = "gpio-mux";
+        #mux-control-cells = <0>;
 
-      mux-gpios = <&gpio 114 GPIO_ACTIVE_HIGH>, <&gpio 115 GPIO_ACTIVE_HIGH>;
+        mux-gpios = <&gpio 114 GPIO_ACTIVE_HIGH>, <&gpio 115 GPIO_ACTIVE_HIGH>;
     };
 
-    clk_mux0: mux-doubler {
-      compatible = "adi,gen_mux";
+    clk_mux {
+        compatible = "adi,gen_mux";
 
-      clocks = <&fixed_clk0>, <&fixed_clk1>, <&fixed_clk2>, <&fixed_clk3>;
-      #clock-cells = <0>;
-      clock-names = "clk_100", "clk_200", "clk_400", "clk_800";
-      clock-output-names = "clk-mux-out";
+        clocks = <&fixed_clk0>, <&fixed_clk1>, <&fixed_clk2>, <&fixed_clk3>;
+        #clock-cells = <0>;
+        clock-names = "clk_100", "clk_200", "clk_400", "clk_800";
+        clock-output-names = "clk-mux-out";
 
-      mux-controls = <&mux0>;
-      mux-state-names = "100M", "200M", "400M", "800M";
+        mux-controls = <&mux>;
+        mux-state-names = "100M", "200M", "400M", "800M";
     };
-
-...
+...