FIX: Bug located in primitives circuit module

doc/changelog.d/6775.fixed.md

@@ -0,0 +1 @@
+Bug located in primitives circuit module

src/ansys/aedt/core/modeler/circuits/primitives_circuit.py

@@ -1387,7 +1387,7 @@ def refresh_all_ids(self):
                         o.schematic_id = int(name[1].split(":")[0])
                         objID = int(o.schematic_id)
                     else:
-                        o.id = int(name[1])
+                        o.id = int(name[1]) if name[1].isdigit() else name[1]
                         o.schematic_id = name[2]
                         objID = int(o.schematic_id)