Merge 3D maze game

Makefile

@@ -192,6 +192,7 @@ ECP_FLASH_OFFSET=0x80000
 toplevel=fpga/top-orangecrab0.2.vhdl
 litedram_target=orangecrab-85-0.2
 soc_extra_v += litesdcard/generated/lattice/litesdcard_core.v
+soc_extra_v += valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.v
 dmi_dtm=dmi_dtm_ecp5.vhdl
 endif
 
@@ -211,7 +212,6 @@ ifneq ($(litedram_target),)
 soc_extra_synth += litedram/extras/litedram-wrapper-l2.vhdl \
 	litedram/generated/$(litedram_target)/litedram-initmem.vhdl
 soc_extra_v += litedram/generated/$(litedram_target)/litedram_core.v
-LITEDRAM_GHDL_ARG=-gUSE_LITEDRAM=true
 endif
 
 GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
@@ -232,7 +232,7 @@ fpga_files = fpga/soc_reset.vhdl \
 
 synth_files = $(core_files) $(soc_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 
-microwatt.json: $(synth_files) $(RAM_INIT_FILE)
+microwatt.json: $(synth_files) $(RAM_INIT_FILE) $(soc_extra_v)
 	$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -abc9 -nowidelut -json $@  $(SYNTH_ECP5_FLAGS)"
 
 microwatt.v: $(synth_files) $(RAM_INIT_FILE)

common.vhdl

@@ -200,7 +200,6 @@ package common is
         priv_mode : std_ulogic;
         big_endian : std_ulogic;
 	stop_mark: std_ulogic;
-        sequential: std_ulogic;
         predicted : std_ulogic;
         pred_ntaken : std_ulogic;
 	nia: std_ulogic_vector(63 downto 0);

fpga/top-orangecrab0.2.vhdl

@@ -23,6 +23,7 @@ entity toplevel is
         LOG_LENGTH         : natural := 0;
         UART_IS_16550      : boolean  := true;
         HAS_UART1          : boolean  := false;
+        HAS_UARTUSB        : boolean  := true;
         USE_LITESDCARD     : boolean := true;
         ICACHE_NUM_LINES   : natural := 64;
         NGPIO              : natural := 0
@@ -35,6 +36,11 @@ entity toplevel is
         pin_gpio_0 : out std_ulogic;
         pin_gpio_1 : in  std_ulogic;
 
+        -- USB signals:
+        usb_d_p    : in std_ulogic;
+        usb_d_n    : in std_ulogic;
+        usb_pullup : out std_ulogic;
+
         -- LEDs
         led0_b  : out std_ulogic;
         led0_g  : out std_ulogic;
@@ -186,6 +192,7 @@ begin
             LOG_LENGTH         => LOG_LENGTH,
             UART0_IS_16550     => UART_IS_16550,
             HAS_UART1          => HAS_UART1,
+            HAS_UARTUSB        => HAS_UARTUSB,
             HAS_SD_CARD        => USE_LITESDCARD,
             ICACHE_NUM_LINES   => ICACHE_NUM_LINES,
             HAS_SHORT_MULT     => true,
@@ -194,12 +201,17 @@ begin
         port map (
             -- System signals
             system_clk        => system_clk,
+            clk_48            => ext_clk,
             rst               => soc_rst,
 
             -- UART signals
             uart0_txd         => pin_gpio_0,
             uart0_rxd         => pin_gpio_1,
 
+            usb_d_p           => usb_d_p,
+            usb_d_n           => usb_d_n,
+            usb_pullup        => usb_pullup,
+
 	    -- UART1 signals
 	    --uart1_txd         => uart_pmod_tx,
 	    --uart1_rxd         => uart_pmod_rx,

fpu.vhdl

@@ -197,7 +197,7 @@ architecture behaviour of fpu is
     -- Each output value is the inverse of the center of the input
     -- range for the value, i.e. entry 0 is 1 / (1 + 1/512),
     -- entry 1 is 1 / (1 + 3/512), etc.
-    signal inverse_table : lookup_table := (
+    constant inverse_table : lookup_table := (
         -- 1/x lookup table
         -- Unit bit is assumed to be 1, so input range is [1, 2)
         18x"3fc01", 18x"3f411", 18x"3ec31", 18x"3e460", 18x"3dc9f", 18x"3d4ec", 18x"3cd49", 18x"3c5b5",

include/console.h

@@ -1,11 +1,24 @@
+#pragma once
+
+#include <stdbool.h>
 #include <stddef.h>
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 void console_init(void);
 void console_set_irq_en(bool rx_irq, bool tx_irq);
 int getchar(void);
+bool console_havechar(void);
 int putchar(int c);
 int puts(const char *str);
 
 #ifndef __USE_LIBC
 size_t strlen(const char *s);
 #endif
+
+#ifdef __cplusplus
+}
+#endif

include/liteuart_console.h

@@ -0,0 +1,18 @@
+#pragma once
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+int usb_getchar(void);
+bool usb_havechar(void);
+int usb_putchar(int c);
+int usb_puts(const char *str);
+void usb_console_init(void);
+
+#ifdef __cplusplus
+}
+#endif

include/microwatt_soc.h

@@ -10,10 +10,13 @@
 #define BRAM_BASE       0x80000000  /* Internal BRAM */
 
 #define SYSCON_BASE	0xc0000000  /* System control regs */
-#define UART_BASE	0xc0002000  /* UART */
+#define UART0_BASE      0xc0002000  /* UART */
+#define UART_BASE       UART0_BASE
+#define UART1_BASE      0xc0003000  /* UART */
 #define XICS_ICP_BASE   0xc0004000  /* Interrupt controller */
 #define XICS_ICS_BASE   0xc0005000  /* Interrupt controller */
 #define SPI_FCTRL_BASE  0xc0006000  /* SPI flash controller registers */
+#define UARTUSB_BASE    0xc0008000  /* ValentyUSB UART */
 #define DRAM_CTRL_BASE	0xc8000000  /* LiteDRAM control registers */
 #define LETH_CSR_BASE	0xc8020000  /* LiteEth CSR registers */
 #define LETH_SRAM_BASE	0xc8030000  /* LiteEth MMIO space */
@@ -26,6 +29,7 @@
  */
 #define IRQ_UART0       0
 #define IRQ_ETHERNET    1
+#define IRQ_UARTUSB     5
 
 /*
  * Register definitions for the syscon registers
@@ -42,6 +46,7 @@
 #define   SYS_REG_INFO_HAS_UART1 		(1ull << 6)
 #define   SYS_REG_INFO_HAS_ARTB                 (1ull << 7)
 #define   SYS_REG_INFO_HAS_LITESDCARD 		(1ull << 8)
+#define   SYS_REG_INFO_HAS_UARTUSB              (1ull << 9)
 #define SYS_REG_BRAMINFO		0x10
 #define   SYS_REG_BRAMINFO_SIZE_MASK		0xfffffffffffffull
 #define SYS_REG_DRAMINFO		0x18

lib/console.c

@@ -148,6 +148,13 @@ int getchar(void)
 	}
 }
 
+bool console_havechar(void) {
+	if (uart_is_std)
+		return !std_uart_rx_empty();
+	else
+		return !potato_uart_rx_empty();
+}
+
 int putchar(int c)
 {
 	if (uart_is_std) {