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@programmerjake programmerjake commented Mar 4, 2022

I added a simple 3D maze game that is a pretty impressive demo of what Microwatt can do.

It's based on #347

cc @mkj

Screenshot of it running on an OrangeCrab:
3D Maze Game on Microwatt on OrangeCrab

mkj and others added 5 commits March 4, 2022 10:49
Signed-off-by: Matt Johnston <[email protected]>
An extra uart is added at 0xc0008000 attached to valentyusb, using
the OrangeCrab's onboard USB port.
This has a liteuart interface, an identifier bit is added to syscon.

Generated from branch hw_cdc_eptri of
https://github.com/litex-hub/valentyusb

The generate script is based on valentyusb/sim/generate_verilog.py

UARTUSB: usbserial@8000 {
        device_type = "serial";
        compatible = "litex,liteuart";
        reg = <0x8000 0x100>;
        interrupts = <0x15 0x1>;
};

(requires extra kernel patches for early console at present v5.16)

Signed-off-by: Matt Johnston <[email protected]>
usb_hello is a copy of hello_world but uses both consoles

Signed-off-by: Matt Johnston <[email protected]>
That makes it easier to override a non-litedram build for testing
RAM_INIT_FILE, eg

make microwatt.dfu  LITEDRAM_GHDL_ARG=-gUSE_LITEDRAM=false  RAM_INIT_FILE=usb_hello/usb_hello.hex

Signed-off-by: Matt Johnston <[email protected]>
I added a simple 3D maze game that is a pretty impressive demo of what Microwatt can do.

It's based on antonblanchard#347

Signed-off-by: Jacob Lifshay <[email protected]>
antonblanchard and others added 11 commits March 15, 2022 16:03
GHDL synthesis is complaining that inverse_table is never stored to.
Change it to a constant.

Signed-off-by: Anton Blanchard <[email protected]>
Use unsigned() to make it clear what we are doing.

Signed-off-by: Anton Blanchard <[email protected]>
GHDL synthesis is flagging a warning about this.

Signed-off-by: Anton Blanchard <[email protected]>
xics: Fix warning when comparing two std_ulogic_vectors
Remove unused sequential signal from Fetch1ToIcacheType
log2ceil() returns the number of bits required to store a value, so we
need to pass in memory_size-1, not memory_size.

Every other user of log2ceil() gets this right.

Signed-off-by: Anton Blanchard <[email protected]>
wishbone_bram_wrapper ram_addr_bits is 1 bit off
This allows us to boot from flash for example.

Signed-off-by: Anton Blanchard <[email protected]>
…ddress

Allow ALT_RESET_ADDRESS to be overridden
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Merged in latest changes from master (thanks, Tobias Platen!)

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4 participants