feat: add ARMv7-A support with page table structures and tests

.github/workflows/ci.yml

@@ -9,7 +9,7 @@ jobs:
       fail-fast: false
       matrix:
         rust-toolchain: [nightly]
-        targets: [x86_64-unknown-linux-gnu, x86_64-unknown-none, riscv64gc-unknown-none-elf, aarch64-unknown-none-softfloat, loongarch64-unknown-none-softfloat]
+        targets: [x86_64-unknown-linux-gnu, x86_64-unknown-none, riscv64gc-unknown-none-elf, aarch64-unknown-none-softfloat, loongarch64-unknown-none-softfloat, armv7a-none-eabi]
     steps:
     - uses: actions/checkout@v4
     - uses: dtolnay/rust-toolchain@nightly

page_table_entry/README.md

@@ -11,17 +11,19 @@ Currently supported architectures and page table entry types:
 
 - x86: [`x86_64::X64PTE`][1]
 - ARM: [`aarch64::A64PTE`][2]
-- RISC-V: [`riscv::Rv64PTE`][3]
-- LoongArch: [`loongarch64::LA64PTE`][4]
+- ARM (32-bit): [`arm::A32PTE`][3]
+- RISC-V: [`riscv::Rv64PTE`][4]
+- LoongArch: [`loongarch64::LA64PTE`][5]
 
-All these types implement the [`GenericPTE`][5] trait, which provides unified
+All these types implement the [`GenericPTE`][6] trait, which provides unified
 methods for manipulating various page table entries.
 
 [1]: https://docs.rs/page_table_entry/latest/page_table_entry/x86_64/struct.X64PTE.html
 [2]: https://docs.rs/page_table_entry/latest/page_table_entry/aarch64/struct.A64PTE.html
-[3]: https://docs.rs/page_table_entry/latest/page_table_entry/riscv/struct.Rv64PTE.html
-[4]: https://docs.rs/page_table_entry/latest/page_table_entry/loongarch64/struct.LA64PTE.html
-[5]: https://docs.rs/page_table_entry/latest/page_table_entry/trait.GenericPTE.html
+[3]: https://docs.rs/page_table_entry/latest/page_table_entry/arm/struct.A32PTE.html
+[4]: https://docs.rs/page_table_entry/latest/page_table_entry/riscv/struct.Rv64PTE.html
+[5]: https://docs.rs/page_table_entry/latest/page_table_entry/loongarch64/struct.LA64PTE.html
+[6]: https://docs.rs/page_table_entry/latest/page_table_entry/trait.GenericPTE.html
 
 ## Examples (x86_64)