Fix PCI SATA link training instability on rock-5-itx#382
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igorpecovnik merged 2 commits intoarmbian:rk-6.1-rkr5.1from Aug 11, 2025
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Fix PCI SATA link training instability on rock-5-itx#382igorpecovnik merged 2 commits intoarmbian:rk-6.1-rkr5.1from
igorpecovnik merged 2 commits intoarmbian:rk-6.1-rkr5.1from
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…n-refclk-mode >From the RK3588 Technical Reference Manual, Part1, section 6.19 PCIe3PHY_GRF Register Description: "rxX_cmn_refclk_mode" RX common reference clock mode for lane X. This mode should be enabled only when the far-end and near-end devices are running with a common reference clock. The hardware reset value for this field is 0x1 (enabled). Note that this register field is only available on RK3588, not on RK3568. The link training either fails or is highly unstable (link state will jump continuously between L0 and recovery) when this mode is enabled while using an endpoint running in Separate Reference Clock with No SSC (SRNS) mode or Separate Reference Clock with SSC (SRIS) mode. (Which is usually the case when using a real SoC as endpoint, e.g. the RK3588 PCIe controller can run in both Root Complex and Endpoint mode.) Add support for the device tree property rockchip,rx-common-refclk-mode, such that the PCIe PHY can be used in configurations where the Root Complex and Endpoint are not using a common reference clock. Signed-off-by: Niklas Cassel <cassel@kernel.org> Link: https://lore.kernel.org/r/20240412125818.17052-3-cassel@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Alban Browaeys <alban.browaeys@gmail.com>
Based on upstream initial dts definition. Signed-off-by: Alban Browaeys <alban.browaeys@gmail.com>
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amazingfate
approved these changes
Aug 11, 2025
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From upstrea:
Disable common refclk for the pcie phy on rock-5-itx.
On Radxa rock-5-itx the SATA endpoint was unstable. Most of the time, the drives attached to it were not detected.
Jira reference number AR-2561 (though this fix is only applied for the vendor kernel on rock-5-itx)