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1. ALU-Verification-UVM ALU-Verification-UVM Public

   A SystemVerilog UVM-based verification environment for validating an Arithmetic Logic Unit (ALU).

   SystemVerilog

2. Synchronous-FIFO Synchronous-FIFO Public

   This repository contains the design and verification of a parameterized synchronous FIFO implemented in SystemVerilog and thoroughly validated using UVM (Universal Verification Methodology).

   SystemVerilog

3. branch-prediction-simulator branch-prediction-simulator Public

   A branch prediction simulator that models how modern CPUs predict branch instructions. It evaluates multiple branch predictor algorithms using offline branch traces, compares predictions against ac…

   C++

4. OSPI-Verification-Framework-UVM OSPI-Verification-Framework-UVM Public

   UVM-based verification of OSPI Controller in SoC designs.

   SystemVerilog

5. APB-Peripheral-Subsystem-Verification APB-Peripheral-Subsystem-Verification Public

   A comprehensive SystemVerilog/UVM testbench verifying an AMBA APB Subsystem containing UART, SPI, and I2C controllers.

   SystemVerilog

6. AXI-Lite-SRAM-Controller-UVM-Verification AXI-Lite-SRAM-Controller-UVM-Verification Public

   UVM Verification of AXI-Lite Sram Controller

   SystemVerilog