ALU Verification using UVM

This project demonstrates the verification of an Arithmetic Logic Unit (ALU) using the Universal Verification Methodology (UVM) in SystemVerilog. It provides a reusable and scalable UVM testbench to validate the functional correctness of ALU operations.

Features

• UVM-based testbench architecture
• Supports arithmetic and logical ALU operations
• Reusable UVM components (driver, monitor, agent, scoreboard)
• Randomized and directed test sequences
• Functional coverage and self-checking scoreboard

ALU Operations Verified

• Addition
• Subtraction
• AND, OR, XOR