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Adding RISCV to supported architectures #83

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Merged
Rot127 merged 9 commits into from
Jan 25, 2026
Merged

Adding RISCV to supported architectures #83

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e41b4b2
Added RISCV to supported architectures and added code to recognize it…
moste00 Jul 17, 2025
ca565fc
added support for primary key index generation and other fixes
moste00 Jul 26, 2025
974f448
added compressed instruction info generation and the necessary fixes
moste00 Aug 23, 2025
2bfe659
final touches to fix the generation of compressed instruction info logic
moste00 Sep 5, 2025
5cbcec6
added isCall flag and generated MEM access for some instructions with…
moste00 Oct 21, 2025
72ca092
[BACKPATCH] fixed problem with c_srli immediates by cherry picking a …
moste00 Oct 22, 2025
ffdfb99
revert bad isCall flag setting
moste00 Dec 23, 2025
95db779
use llvm regex instead of C++ stdlib regex, various cleanups and revi…
moste00 Jan 8, 2026
59d548d
revert extraneous formatting
moste00 Jan 18, 2026
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21 changes: 21 additions & 0 deletions llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -276,6 +276,19 @@ static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
return MCDisassembler::Success;
}

static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm,
int64_t Address,
const MCDisassembler *Decoder) {
assert(isUInt<6>(Imm) && "Invalid immediate");

if (!Decoder->getSubtargetInfo().hasFeature(RISCV::Feature64Bit) &&
!isUInt<5>(Imm))
return MCDisassembler::Fail;

Inst.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}

template <unsigned N>
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
int64_t Address,
Expand All @@ -285,6 +298,14 @@ static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
}

static DecodeStatus
decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address,
const MCDisassembler *Decoder) {
if (Imm == 0)
return MCDisassembler::Fail;
return decodeUImmLog2XLenOperand(Inst, Imm, Address, Decoder);
}

template <unsigned N>
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
int64_t Address,
Expand Down
11 changes: 5 additions & 6 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -191,8 +191,7 @@ def uimmlog2xlen : RISCVOp, ImmLeaf<XLenVT, [{
return isUInt<5>(Imm);
}]> {
let ParserMatchClass = UImmLog2XLenAsmOperand;
// TODO: should ensure invalid shamt is rejected when decoding.
let DecoderMethod = "decodeUImmOperand<6>";
let DecoderMethod = "decodeUImmLog2XLenOperand";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
Expand Down Expand Up @@ -611,12 +610,12 @@ def AUIPC : RVInstU<OPC_AUIPC, (outs GPR:$rd), (ins uimm20_auipc:$imm20),
"auipc", "$rd, $imm20">, Sched<[WriteIALU]>;

def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0_jal:$imm20),
"jal", "$rd, $imm20">, Sched<[WriteJal]>;
"jal", "$rd, $imm20">, Sched<[WriteJal]>;

def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
(ins GPR:$rs1, simm12:$imm12),
"jalr", "$rd, ${imm12}(${rs1})">,
Sched<[WriteJalr, ReadJalr]>;
(ins GPR:$rs1, simm12:$imm12),
"jalr", "$rd, ${imm12}(${rs1})">,
Sched<[WriteJalr, ReadJalr]>;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0

def BEQ : BranchCC_rri<0b000, "beq">;
Expand Down
3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoC.td
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Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,7 @@ def uimmlog2xlennonzero : RISCVOp, ImmLeaf<XLenVT, [{
return isUInt<5>(Imm) && (Imm != 0);
}]> {
let ParserMatchClass = UImmLog2XLenNonZeroAsmOperand;
// TODO: should ensure invalid shamt is rejected when decoding.
let DecoderMethod = "decodeUImmNonZeroOperand<6>";
let DecoderMethod = "decodeUImmLog2XLenNonZeroOperand";
let OperandType = "OPERAND_UIMMLOG2XLEN_NONZERO";
let MCOperandPredicate = [{
int64_t Imm;
Expand Down
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