Add NestedAssignmentPattern test

tests/NestedAssignmentPattern/Makefile.in

@@ -0,0 +1,2 @@
+TOP_FILE := $(TEST_DIR)/top.sv
+TOP_MODULE := top

tests/NestedAssignmentPattern/main.cpp

@@ -0,0 +1,40 @@
+#include <iostream>
+#include <verilated_vcd_c.h>
+
+#define VL_DEBUG
+#include "Vtop.h"
+#include "verilated.h"
+
+static vluint64_t main_time = 0;
+
+double
+sc_time_stamp()
+{
+  return main_time;
+}
+
+int main (int argc, char **argv) {
+  Verilated::commandArgs(argc, argv);
+  Vtop *top = new Vtop();
+
+  Verilated::traceEverOn(true);
+  VerilatedVcdC* tfp = new VerilatedVcdC;
+  top->trace(tfp, 99);
+  tfp->open("dump.vcd");
+
+  while (!Verilated::gotFinish() && (main_time < 100)) {
+    top->eval();
+    tfp->dump(main_time);
+
+    main_time += 1;
+
+    std::cout << "time: " << main_time
+      << " b: " << (top->b?1:0)
+      << std::endl;
+  }
+  top->final();
+  tfp->close();
+    delete top;
+
+  return 0;
+}

tests/NestedAssignmentPattern/top.sv

@@ -0,0 +1,15 @@
+module top(output [3:0] b);
+  typedef struct packed {
+    logic [1:0] addr;
+    logic sel;
+    logic rd;
+  } complex_t;
+
+  parameter complex_t RSP_DEFAULT = '{
+    addr: '{default: '1},
+    sel: 1'b0,
+    rd: 1'b1
+  };
+  assign b = RSP_DEFAULT;
+
+endmodule

tests/NestedAssignmentPattern/yosys_script

@@ -0,0 +1,6 @@
+plugin -i uhdm
+read_uhdm -debug top.uhdm
+prep -top \top
+write_verilog
+write_verilog yosys.sv
+sim -rstlen 10 -vcd dump.vcd