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@rowanG077 rowanG077 commented Feb 10, 2026

  • Write a changelog entry (see changelog/README.md)
  • Check copyright notices are up to date in edited files

@rowanG077 rowanG077 force-pushed the 3147-verilog-blackbox-for-iteratei-uses-wire-for-sequential-assignments branch from 755916f to c52cf26 Compare February 10, 2026 18:30
@rowanG077 rowanG077 changed the title FIXED: HO blackboxes not propagating usage metadata Fix HO blackboxes not propagating usage metadata Feb 10, 2026
@rowanG077 rowanG077 requested a review from lmbollen February 10, 2026 18:33
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rowanG077 commented Feb 10, 2026

Sad to say neither verilator or yosys catch this as a warning. And just text based checks really sucks because on my machine this text based check passes but I guess with different GHC/Clash combinations the exact ordering can be different.

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Verilog blackbox for iterateI uses wire for sequential assignments

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