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Update components and traffgen scripts for dramcache tests#1

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aakahlow wants to merge 5 commits intodcache_baseline_componentsfrom
dcache_updated_components
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Update components and traffgen scripts for dramcache tests#1
aakahlow wants to merge 5 commits intodcache_baseline_componentsfrom
dcache_updated_components

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@aakahlow aakahlow commented Oct 1, 2021

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@aakahlow aakahlow force-pushed the dcache_updated_components branch from c472d3e to 0c32710 Compare October 1, 2021 00:17
Change-Id: I1ce799c0321b2e1c7fc296b4e62494de348bd7a6
Change-Id: I60b9be20100995fb9bb241e51885c88f6facead9
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This change hasn't consumed the upstream develop changes where component_library was moved to src/. This change will mostly just change what you have to import in the components part. In fact, you can keep most of your code exactly where it is. Though, I think I would do it like this:

my_components/
  memory/
    dc_interface/
      ddr3.py
      ddr4.py
....

There's a few extra files here, but otherwise, it looks great to me! I'm glad the components worked out here!

from m5.objects import DRAMInterface


class GDDR5_4000_2x32(DRAMInterface):
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I guess this file isn't needed if it's not using the DRAMDCInterface?

"""


class HMC_2500_1x32(DDR3_1600_8x8):
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I don't think this is useful. HMC is weird, not well supported in gem5, and not appropriate for this kind of DRAM cache anyway.

from m5.objects import DRAMInterface


class LPDDR2_S4_1066_1x32(DRAMInterface):
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Unneeded?

from m5.objects import DRAMInterface


class LPDDR3_1600_1x32(DRAMInterface):
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Unneeded?

from m5.objects import DRAMInterface


class LPDDR5_5500_1x16_BG_BL32(DRAMInterface):
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Unneeded?

from m5.objects import DRAMInterface


class WideIO_200_1x128(DRAMInterface):
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Unneeded?

size_nvm)


def SingleChannelLPDDR3_1600_NVM_2400_1x64(
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I don't think this will work because LPDDR3 isn't a DRAMDCInterface, right?

Also, LPDDR3 is super ancient and not appropriate for this kind of research. Maybe LPDDR5 or 4X, but not 3.

rate=args.rate,
min_addr=min_addr,
max_addr=max_addr,
rd_perc=args.rd_perc,
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Should this be fixed upstream? If so, let's do it now.

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I am not able to find these scripts upstream. Mahyar had referred me to one of his repos, where this change might be needed

Change-Id: Ieaf84ab6b176c53fd0182f8af86ac7617f98be4f
@aakahlow
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This change hasn't consumed the upstream develop changes where component_library was moved to src/. This change will mostly just change what you have to import in the components part. In fact, you can keep most of your code exactly where it is. Though, I think I would do it like this:

my_components/
  memory/
    dc_interface/
      ddr3.py
      ddr4.py
....

There's a few extra files here, but otherwise, it looks great to me! I'm glad the components worked out here!

Sorry, I took very long to push the changes. I have removed all the unneeded files. As far as moving the components location is concerned, I think it might be a better idea to do while rebasing this branch/repo, so that other changes in components can be taken care of.

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