Hbm components

configs-mem-test/mem_info.py

@@ -0,0 +1,26 @@
+
+from gem5.components.memory import DualChannelDDR4_2400
+from gem5.components.memory import SingleChannelDDR3_1600
+from gem5.components.memory import SingleChannelDDR4_2400
+from gem5.components.memory import SingleChannelLPDDR3_1600
+from gem5.components.memory import SingleChannelHBM
+from gem5.components.memory import SingleChannelHBM_DDR3
+from gem5.components.memory import SingleChannelHBMPseudo
+from gem5.components.memory import HBM2Stack
+from gem5.components.memory import HBM2Stackv2
+
+def GetMemClass(simulator, mem_type):
+    return MemInfoDict[simulator][mem_type]
+
+MemInfoDict = {
+    'gem5' : {
+        'ddr3' : SingleChannelDDR3_1600,
+        'ddr4' : SingleChannelDDR4_2400,
+        'lpddr3' : SingleChannelLPDDR3_1600,
+        'hbm' : SingleChannelHBM,
+        'hbm_pseudo' : SingleChannelHBMPseudo,
+        'hbm_from_ddr3' : SingleChannelHBM_DDR3,
+        'hbm_stack' : HBM2Stack,
+        'hbm_stack_v2' : HBM2Stackv2
+    }
+}

configs-mem-test/run_memory_test.py

@@ -0,0 +1,114 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import m5
+import sys
+import argparse
+
+from m5.objects import *
+
+from m5.util import fatal
+from m5.objects import Root
+from mem_info import GetMemClass
+
+from gem5.components.boards.test_board import TestBoard
+from gem5.components.cachehierarchies.classic.no_cache import NoCache
+from gem5.components.processors.linear_generator import LinearGenerator
+from gem5.components.processors.random_generator import RandomGenerator
+
+parser = argparse.ArgumentParser()
+parser.add_argument("mem_type", type=str, help="type of memory to simulate")
+parser.add_argument(
+    "simulator", type=str, help="the simulator to use for memory"
+)
+parser.add_argument("mode", type=str, help="type of traffic to use")
+parser.add_argument(
+    "duration",
+    type=str,
+    help="duration for which the synthetic traffic will be generated",
+)
+parser.add_argument(
+    "rate",
+    type=str,
+    help="the rate at which the synthetic traffic will be generated",
+)
+parser.add_argument(
+    "rd_perc",
+    type=int,
+    help="specifies the percentage of read request in the generated traffic",
+)
+
+args = parser.parse_args()
+
+args.rate = args.rate + "GB/s"
+
+memory_class = GetMemClass(args.simulator, args.mem_type)
+memory = memory_class()
+
+cache_hierarchy = NoCache()
+
+#range=AddrRange('8GB')
+
+mem_range = AddrRange(memory.get_size())
+
+min_addr = mem_range.start
+max_addr = mem_range.end
+
+if args.mode == "linear":
+    generator = LinearGenerator(
+        num_cores=1,
+        duration=args.duration,
+        rate=args.rate,
+        min_addr=min_addr,
+        max_addr=max_addr,
+        rd_perc=args.rd_perc,
+    )
+elif args.mode == "random":
+    generator = RandomGenerator(
+        num_cores=1,
+        duration=args.duration,
+        rate=args.rate,
+        min_addr=min_addr,
+        max_addr=max_addr,
+        rd_perc=args.rd_perc,
+    )
+else:
+    fatal("Generator type not supported")
+
+motherboard = TestBoard(
+    clk_freq="4GHz",
+    processor=generator,
+    memory=memory,
+    cache_hierarchy=cache_hierarchy,
+)
+#motherboard.connect_things()
+
+root = Root(full_system=False, system=motherboard)
+m5.instantiate()
+generator.start_traffic()
+print("Beginning simulation!")
+exit_event = m5.simulate()
+print("Exiting @ tick %i because %s" % (m5.curTick(), exit_event.getCause()))

src/python/gem5/components/memory/__init__.py

@@ -29,8 +29,11 @@
 from .single_channel import SingleChannelDDR4_2400
 from .single_channel import SingleChannelHBM
 from .single_channel import SingleChannelLPDDR3_1600
+from .single_channel import SingleChannelHBM_DDR3
+from .single_channel import SingleChannelHBMPseudo
 from .multi_channel import DualChannelDDR3_1600
 from .multi_channel import DualChannelDDR3_2133
 from .multi_channel import DualChannelDDR4_2400
 from .multi_channel import HBM2Stack
+from .multi_channel import HBM2Stackv2
 from .multi_channel import DualChannelLPDDR3_1600

src/python/gem5/components/memory/dram_interfaces/hbm.py

@@ -194,3 +194,103 @@ class HBM_1000_4H_1x64(HBM_1000_4H_1x128):
 
     # self refresh exit time
     tXS = "65ns"
+
+# This is a hypothetical HBM interface based on DDR3
+# Increases the clock of DDR3 by 10x
+# Decreases burst length (and increaes device
+# bus width) by 2x
+class HBM_FROM_DDR3(DRAMInterface):
+    # size of device in bytes
+    device_size = '512MiB'
+
+    device_bus_width = 16
+
+    # Using a burst length of 4
+    burst_length = 4
+
+    # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
+    device_rowbuffer_size = '1KiB'
+
+    # 8x8 configuration, so 8 devices
+    devices_per_rank = 8
+
+    # Use two ranks
+    ranks_per_channel = 2
+
+    # DDR3 has 8 banks in all configurations
+    banks_per_rank = 8
+
+    # 8000 MHz
+    tCK = '0.125ns'
+
+    # 4 beats across an x64 interface translates to 2 clocks @ 8000 MHz
+    tBURST = '0.25ns'
+
+    # Keeping the other times same as DDR3
+    # DDR3-1600 11-11-11
+    tRCD = '13.75ns'
+    tCL = '13.75ns'
+    tRP = '13.75ns'
+    tRAS = '35ns'
+    tRRD = '6ns'
+    tXAW = '30ns'
+    activation_limit = 4
+    tRFC = '260ns'
+
+    tWR = '15ns'
+
+    # Greater of 4 CK or 7.5 ns
+    tWTR = '7.5ns'
+
+    # Greater of 4 CK or 7.5 ns
+    tRTP = '7.5ns'
+
+    # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
+    tRTW = '2.5ns'
+
+    # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
+    tCS = '2.5ns'
+
+    # <=85C, half for >85C
+    tREFI = '7.8us'
+
+    # active powerdown and precharge powerdown exit time
+    tXP = '6ns'
+
+    # self refresh exit time
+    tXS = '270ns'
+
+    # Current values from datasheet Die Rev E,J
+    IDD0 = '55mA'
+    IDD2N = '32mA'
+    IDD3N = '38mA'
+    IDD4W = '125mA'
+    IDD4R = '157mA'
+    IDD5 = '235mA'
+    IDD3P1 = '38mA'
+    IDD2P1 = '32mA'
+    IDD6 = '20mA'
+    VDD = '1.5V'
+
+    read_buffer_size = 1024
+    write_buffer_size = 1024
+
+class HBM_1000_4H_1x64_pseudo(HBM_1000_4H_1x64):
+    """
+    This is an approximation of HBM_1000_4H_1x64
+    single channel (with two pseudo channels)
+    decreases the burst length by 2x -->
+    increases the bus width to maintain an atom
+    size of 64 bytes
+    increases clock frequency by 2x (is 
+    that needed?)
+    """
+
+    device_bus_width = 128
+    burst_length = 2
+
+    tCK = "1ns"
+    tBURST = "2ns"
+
+
+

src/python/gem5/components/memory/multi_channel.py

@@ -32,7 +32,7 @@
 from .dram_interfaces.ddr4 import DDR4_2400_8x8
 from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32
 from .dram_interfaces.hbm import HBM_1000_4H_1x64
-
+from .dram_interfaces.hbm import HBM_1000_4H_1x64_pseudo
 
 def DualChannelDDR3_1600(
     size: Optional[str] = None,
@@ -94,3 +94,15 @@ def HBM2Stack(
         64,
         size=size,
     )
+
+def HBM2Stackv2(
+    size: Optional[str] = None,
+) -> AbstractMemorySystem:
+    if not size:
+        size = "4GiB"
+    return ChanneledMemory(
+        HBM_1000_4H_1x64_pseudo,
+        8,
+        64,
+        size=size,
+    )

src/python/gem5/components/memory/single_channel.py

@@ -33,7 +33,8 @@
 from .dram_interfaces.hbm import HBM_1000_4H_1x128
 from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32
 from .dram_interfaces.ddr3 import DDR3_1600_8x8, DDR3_2133_8x8
-
+from .dram_interfaces.hbm import HBM_FROM_DDR3
+from .dram_interfaces.hbm import HBM_1000_4H_1x64_pseudo
 
 def SingleChannelDDR3_1600(
     size: Optional[str] = None,
@@ -95,3 +96,27 @@ def SingleChannelHBM(
         64,
         size=size
     )
+
+def SingleChannelHBM_DDR3(
+    size: Optional[str] = None,
+) -> AbstractMemorySystem:
+    if not size:
+        size = "4GiB"
+    return ChanneledMemory(
+        HBM_FROM_DDR3,
+        1,
+        64,
+        size=size
+    )
+
+def SingleChannelHBMPseudo(
+    size: Optional[str] = None,
+) -> AbstractMemorySystem:
+    if not size:
+        size = "256MiB"
+    return ChanneledMemory(
+        HBM_1000_4H_1x64_pseudo,
+        1,
+        64,
+        size=size
+    )