Adds SimpleMemCtrl and MemCtrl

src/mem/DRAMInterface.py

@@ -48,7 +48,7 @@ class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
 
 class DRAMInterface(MemInterface):
     type = 'DRAMInterface'
-    cxx_header = "mem/mem_interface.hh"
+    cxx_header = "mem/dram_interface.hh"
     cxx_class = 'gem5::memory::DRAMInterface'
 
     # scheduler page policy

src/mem/MemCtrl.py

@@ -40,54 +40,12 @@
 
 from m5.params import *
 from m5.proxy import *
-from m5.objects.QoSMemCtrl import *
+from m5.objects.SimpleMemCtrl import *
 
-# Enum for memory scheduling algorithms, currently First-Come
-# First-Served and a First-Row Hit then First-Come First-Served
-class MemSched(Enum): vals = ['fcfs', 'frfcfs']
-
-# MemCtrl is a single-channel single-ported Memory controller model
-# that aims to model the most important system-level performance
-# effects of a memory controller, interfacing with media specific
-# interfaces
-class MemCtrl(QoSMemCtrl):
+class MemCtrl(SimpleMemCtrl):
     type = 'MemCtrl'
     cxx_header = "mem/mem_ctrl.hh"
     cxx_class = 'gem5::memory::MemCtrl'
 
-    # single-ported on the system interface side, instantiate with a
-    # bus in front of the controller for multiple ports
-    port = ResponsePort("This port responds to memory requests")
-
-    # Interface to volatile, DRAM media
-    dram = Param.DRAMInterface(NULL, "DRAM interface")
-
-    # Interface to non-volatile media
-    nvm = Param.NVMInterface(NULL, "NVM interface")
-
-    # read and write buffer depths are set in the interface
-    # the controller will read these values when instantiated
-
-    # threshold in percent for when to forcefully trigger writes and
-    # start emptying the write buffer
-    write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
-
-    # threshold in percentage for when to start writes if the read
-    # queue is empty
-    write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
-
-    # minimum write bursts to schedule before switching back to reads
-    min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
-                                           "switching to reads")
-
-    # scheduler, address map and page policy
-    mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
-
-    # pipeline latency of the controller and PHY, split into a
-    # frontend part and a backend part, with reads and writes serviced
-    # by the queues only seeing the frontend contribution, and reads
-    # serviced by the memory seeing the sum of the two
-    static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
-    static_backend_latency = Param.Latency("10ns", "Static backend latency")
-
-    command_window = Param.Latency("10ns", "Static backend latency")
+    # Interface to memory media
+    nvm = Param.NVMInterface(NULL, "Memory interface")

src/mem/NVMInterface.py

@@ -44,7 +44,7 @@
 # are modeled without getting into too much detail of the media itself.
 class NVMInterface(MemInterface):
     type = 'NVMInterface'
-    cxx_header = "mem/mem_interface.hh"
+    cxx_header = "mem/nvm_interface.hh"
     cxx_class = 'gem5::memory::NVMInterface'
 
     # NVM DIMM could have write buffer to offload writes

src/mem/SConscript

@@ -48,7 +48,9 @@ SimObject('AddrMapper.py', sim_objects=['AddrMapper', 'RangeAddrMapper'])
 SimObject('Bridge.py', sim_objects=['Bridge'])
 SimObject('SysBridge.py', sim_objects=['SysBridge'])
 DebugFlag('SysBridge')
-SimObject('MemCtrl.py', sim_objects=['MemCtrl'], enums=['MemSched'])
+SimObject('SimpleMemCtrl.py', sim_objects=['SimpleMemCtrl'],
+        enums=['MemSched'])
+SimObject('MemCtrl.py', sim_objects=['MemCtrl'])
 SimObject('MemInterface.py', sim_objects=['MemInterface'], enums=['AddrMap'])
 SimObject('DRAMInterface.py', sim_objects=['DRAMInterface'],
         enums=['PageManage'])
@@ -73,8 +75,11 @@ Source('cfi_mem.cc')
 Source('drampower.cc')
 Source('external_master.cc')
 Source('external_slave.cc')
+Source('simple_mem_ctrl.cc')
 Source('mem_ctrl.cc')
 Source('mem_interface.cc')
+Source('dram_interface.cc')
+Source('nvm_interface.cc')
 Source('noncoherent_xbar.cc')
 Source('packet.cc')
 Source('port.cc')
@@ -127,6 +132,7 @@ CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
 
 DebugFlag('Bridge')
 DebugFlag('CommMonitor')
+DebugFlag('MemIntr')
 DebugFlag('DRAM')
 DebugFlag('DRAMPower')
 DebugFlag('DRAMState')

src/mem/SimpleMemCtrl.py

@@ -0,0 +1,90 @@
+# Copyright (c) 2012-2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2013 Amin Farmahini-Farahani
+# Copyright (c) 2015 University of Kaiserslautern
+# Copyright (c) 2015 The University of Bologna
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.params import *
+from m5.proxy import *
+from m5.objects.QoSMemCtrl import *
+
+# Enum for memory scheduling algorithms, currently First-Come
+# First-Served and a First-Row Hit then First-Come First-Served
+class MemSched(Enum): vals = ['fcfs', 'frfcfs']
+
+# SimpleMemCtrl is a single-channel single-ported Memory controller model
+# that aims to model the most important system-level performance
+# effects of a memory controller, interfacing with media specific
+# interfaces
+class SimpleMemCtrl(QoSMemCtrl):
+    type = 'SimpleMemCtrl'
+    cxx_header = "mem/simple_mem_ctrl.hh"
+    cxx_class = 'gem5::memory::SimpleMemCtrl'
+
+    # single-ported on the system interface side, instantiate with a
+    # bus in front of the controller for multiple ports
+    port = ResponsePort("This port responds to memory requests")
+
+    # Interface to memory media
+    dram = Param.MemInterface(NULL, "Memory interface")
+
+    # read and write buffer depths are set in the interface
+    # the controller will read these values when instantiated
+
+    # threshold in percent for when to forcefully trigger writes and
+    # start emptying the write buffer
+    write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
+
+    # threshold in percentage for when to start writes if the read
+    # queue is empty
+    write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
+
+    # minimum write bursts to schedule before switching back to reads
+    min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
+                                           "switching to reads")
+
+    # scheduler, address map and page policy
+    mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
+
+    # pipeline latency of the controller and PHY, split into a
+    # frontend part and a backend part, with reads and writes serviced
+    # by the queues only seeing the frontend contribution, and reads
+    # serviced by the memory seeing the sum of the two
+    static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
+    static_backend_latency = Param.Latency("10ns", "Static backend latency")
+
+    command_window = Param.Latency("10ns", "Static backend latency")