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* Enable interrupts, set up the mtvec, and print a simple#26

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schirice wants to merge 3 commits intomasterfrom
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* Enable interrupts, set up the mtvec, and print a simple#26
schirice wants to merge 3 commits intomasterfrom
iq-handle

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@schirice schirice commented May 4, 2021

debug msg when a trap occurs so we know the mtval, mepc, and mcause.

 debug msg when a trap occurs so we know the mtval, mepc, and mcause.
@schirice schirice requested review from aroelke and arunthomas May 4, 2021 13:31

void bad_trap(){
unsigned long mepc, mtval, mcause;
asm volatile("csrr %0, mcause" : "=r"(mcause));
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Why not use read_csr here (and the below lines)?

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No reason, I could ... less code being generated this way though.

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