* Enable interrupts, set up the mtvec, and print a simple

iveia/Makefile

@@ -8,13 +8,15 @@ RISCV_ARCH 			 ?= rv32ima
 RISCV_ABI        ?= ilp32
 CFLAGS += --target=riscv32-unknown-elf
 CFLAGS += -DCPU_CLOCK_HZ=50000000
+CFLAGS += -DRV32
 else
 RISCV_ARCH ?= rv64imafd
 RISCV_ABI ?= lp64d
 
 CFLAGS += --target=riscv64-unknown-elf
 CFLAGS += -mcmodel=medany
 CFLAGS += -DCPU_CLOCK_HZ=50000000
+CFLAGS += -DRV64
 endif
 
 CFLAGS += -O0 -g3 -Wall -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)

iveia/bsp.h

@@ -1,27 +1,39 @@
 #ifndef RISCV_P2_BSP_H
 #define RISCV_P2_BSP_H
 
+#include "memory_map.h"
+
 #ifndef CPU_CLOCK_HZ
 #define CPU_CLOCK_HZ 50000000
 #endif
 
 /**
  * UART defines
  */
-#define XPAR_XUARTNS550_NUM_INSTANCES 2
+#define XPAR_XUARTNS550_NUM_INSTANCES 3
 #define XPAR_DEFAULT_BAUD_RATE 115200
 
 #define BSP_USE_UART0 1
 #define XPAR_UARTNS550_0_DEVICE_ID 0
 #define XPAR_UARTNS550_0_BAUD_RATE XPAR_DEFAULT_BAUD_RATE
-#define XPAR_UARTNS550_0_BASEADDR 0xA0000000ULL
+#define XPAR_UARTNS550_0_BASEADDR SOC_ADDR_UART0
+// #define XPAR_UARTNS550_0_BASEADDR 0xA0000000ULL
 #define XPAR_UARTNS550_0_CLOCK_HZ CPU_CLOCK_HZ
 
 // UART1 is in use by the PEX, so avoid re-initializing it on the AP
 #define BSP_USE_UART1 0
 #define XPAR_UARTNS550_1_DEVICE_ID 1
 #define XPAR_UARTNS550_1_BAUD_RATE XPAR_DEFAULT_BAUD_RATE
-#define XPAR_UARTNS550_1_BASEADDR (0xA0010000ULL)
+#define XPAR_UARTNS550_1_BASEADDR SOC_ADDR_UART1
+//#define XPAR_UARTNS550_1_BASEADDR (0xA0010000ULL)
 #define XPAR_UARTNS550_1_CLOCK_HZ CPU_CLOCK_HZ
 
+// UART2 is used by the AP as transport
+#define BSP_USE_UART2 1
+#define XPAR_UARTNS550_2_DEVICE_ID 2
+#define XPAR_UARTNS550_2_BAUD_RATE XPAR_DEFAULT_BAUD_RATE
+#define XPAR_UARTNS550_2_BASEADDR SOC_ADDR_UART2
+// #define XPAR_UARTNS550_2_BASEADDR 0xA0020000ULL
+#define XPAR_UARTNS550_2_CLOCK_HZ CPU_CLOCK_HZ
+
 #endif /* RISCV_P2_BSP_H */

iveia/uart.c

@@ -53,108 +53,48 @@ static XUartNs550 UartNs550_1;
 struct UartDriver Uart1;
 #endif
 
+#if BSP_USE_UART2
+static XUartNs550 UartNs550_2;
+struct UartDriver Uart2;
+#endif
+
 /*****************************************************************************/
 /* Peripheral specific definitions */
 #if BSP_USE_UART0
 /**
  * Initialize UART 0 peripheral
  */
-void uart0_init(void)
-{
-    uart_init(&Uart0, XPAR_UARTNS550_0_DEVICE_ID, 0);
-}
-
-/**
- * Return 1 if UART0 has at leas 1 byte in the RX FIFO
- */
-bool uart0_rxready(void)
-{
-    return uart_rxready(&Uart0);
-}
-
-/**
- * Receive a single byte. Polling mode, waits until finished
- */
-char uart0_rxchar(void)
-{
-    return (char)uart_rxchar(&Uart0);
-}
-
-/**
- * Transmit a buffer. Waits indefinitely for a UART TX mutex,
- * returns number of transferred bytes or -1 in case of an error.
- * Synchronous API.
- */
-int uart0_txbuffer(char *ptr, int len)
-{
-    return uart_txbuffer(&Uart0, (uint8_t *)ptr, len);
-}
-
-/**
- * Transmit a single byte. Polling mode, waits until finished
- */
-char uart0_txchar(char c)
-{
-    return (char)uart_txchar(&Uart0, (uint8_t)c);
-}
+UART_INIT(0)
+UART_RXREADY(0)
+UART_RXCHAR(0)
+UART_TXCHAR(0)
+UART_TXBUFFER(0)
+UART_RXBUFFER(0)
 
-int uart0_rxbuffer(char *ptr, int len)
-{
-    return uart_rxbuffer(&Uart0, (uint8_t *)ptr, len);
-}
 #endif /* BSP_USE_UART0 */
 
 #if BSP_USE_UART1
-/**
- * Initialize UART 1 peripheral
- */
-void uart1_init(void)
-{
-    uart_init(&Uart1, XPAR_UARTNS550_1_DEVICE_ID, 0);
-}
 
-/**
- * Return 1 if UART1 has at leas 1 byte in the RX FIFO
- */
-bool uart1_rxready(void)
-{
-    return uart_rxready(&Uart1);
-}
+UART_INIT(1)
+UART_RXREADY(1)
+UART_RXCHAR(1)
+UART_TXCHAR(1)
+UART_TXBUFFER(1)
+UART_RXBUFFER(1)
 
-/**
- * Receive a single byte.
- */
-char uart1_rxchar(void)
-{
-    return (char)uart_rxchar(&Uart1);
-}
+#endif /* BSP_USE_UART1 */
 
-/**
- * Transmit a buffer. Waits indefinitely for a UART TX mutex,
- * returns number of transferred bytes or -1 in case of an error.
- * Synchronous API.
- */
-int uart1_txbuffer(char *ptr, int len)
-{
-    return uart_txbuffer(&Uart1, (uint8_t *)ptr, len);
-}
+#if BSP_USE_UART2
 
-/**
- * Transmit a single byte.
- */
-char uart1_txchar(char c)
-{
-    return (char)uart_txchar(&Uart1, (uint8_t)c);
-}
+UART_INIT(2)
+UART_RXREADY(2)
+UART_RXCHAR(2)
+UART_TXCHAR(2)
+UART_TXBUFFER(2)
+UART_RXBUFFER(2)
+
+#endif /* BSP_USE_UART2 */
 
-/**
- * Transmit buffer.
- */
-int uart1_rxbuffer(char *ptr, int len)
-{
-    return uart_rxbuffer(&Uart1, (uint8_t *)ptr, len);
-}
-#endif /* BSP_USE_UART1 */
 
 /*****************************************************************************/
 /* Driver specific defintions */
@@ -180,6 +120,11 @@ static void uart_init(struct UartDriver *Uart, uint8_t device_id, uint8_t plic_s
     case 1:
         Uart->Device = UartNs550_1;
         break;
+#endif
+#if BSP_USE_UART2
+    case 2:
+        Uart->Device = UartNs550_2;
+        break;
 #endif
     default:
         // Trigger a fault: unsupported device ID

iveia/uart.h

@@ -4,6 +4,48 @@
 #include "bsp.h"
 #include <stdbool.h>
 
+/**
+ * Initialize UART peripheral
+ */
+#define UART_INIT(uart_number)	    \
+  void uart##uart_number##_init(void) \
+  { uart_init(&Uart ## uart_number, XPAR_UARTNS550_ ## uart_number ## _DEVICE_ID , 0); }
+
+/**
+ * Return 1 if UART has at leas 1 byte in the RX FIFO
+ */
+#define UART_RXREADY(uart_number) \
+  bool uart##uart_number##_rxready(void) \
+  {return uart_rxready(&Uart##uart_number);}
+
+/**
+ * Receive a single byte. Polling mode, waits until finished
+ */
+#define UART_RXCHAR(uart_number) \
+  char uart ## uart_number ## _rxchar(void) \
+  { return (char)uart_rxchar(&Uart##uart_number);}
+
+/**
+ * Transmit a single byte. Polling mode, waits until finished
+ */
+#define UART_TXCHAR(uart_number) \
+  char uart##uart_number##_txchar(char c) \
+  { return (char)uart_txchar(&Uart##uart_number, (uint8_t)c); }
+/**
+ * Transmit a buffer. Waits indefinitely for a UART TX mutex,
+ * returns number of transferred bytes or -1 in case of an error.
+ * Synchronous API.
+ */
+#define UART_TXBUFFER(uart_number) \
+  int uart##uart_number##_txbuffer(char *ptr, int len) \
+  { return uart_txbuffer(&Uart##uart_number, (uint8_t *)ptr, len); }
+
+
+#define UART_RXBUFFER(uart_number) \
+  int uart##uart_number##_rxbuffer(char *ptr, int len) \
+  { return uart_rxbuffer(&Uart##uart_number, (uint8_t *)ptr, len);}
+
+
 #if BSP_USE_UART0
 bool uart0_rxready(void);
 char uart0_rxchar(void);
@@ -22,4 +64,13 @@ int uart1_txbuffer(char *ptr, int len);
 void uart1_init(void);
 #endif
 
+#if BSP_USE_UART2
+bool uart2_rxready(void);
+char uart2_rxchar(void);
+char uart2_txchar(char c);
+int uart2_rxbuffer(char *ptr, int len);
+int uart2_txbuffer(char *ptr, int len);
+void uart2_init(void);
+#endif
+
 #endif

iveia/xilinx/uartns550/xuartns550_g.c

@@ -83,6 +83,12 @@ XUartNs550_Config XUartNs550_ConfigTable[] =
 		XPAR_UARTNS550_1_BASEADDR,
 		XPAR_UARTNS550_1_CLOCK_HZ,
 		XPAR_UARTNS550_1_BAUD_RATE
-	}
+	},
+	{
+                XPAR_UARTNS550_2_DEVICE_ID,
+                XPAR_UARTNS550_2_BASEADDR,
+                XPAR_UARTNS550_2_CLOCK_HZ,
+                XPAR_UARTNS550_2_BAUD_RATE
+        }
 };
 /** @} */

vcu118/boot.S

@@ -73,7 +73,8 @@
 /* Startup code */
 .globl boot
 boot:
-    li t6, 0x1800
+	// enable MSTATUS_PRV1 and MSTATUS_MIE
+    li t6, 0x1888
     csrw mstatus, t6
     j _mstart
 

vcu118/init.c

@@ -3,12 +3,30 @@
 
 extern int main(void);
 
+#define write_csr(reg, val) \
+  asm volatile ("csrw " #reg ", %0" :: "r"(val))
+
+#define read_csr(reg) ({ unsigned long __tmp;               \
+            asm volatile ("csrr %0, " #reg : "=r"(__tmp));  \
+            __tmp; })
+
+void bad_trap(){
+  unsigned long mepc, mtval, mcause;
+  asm volatile("csrr %0, mcause" : "=r"(mcause));
+  asm volatile("csrr %0, mtval" : "=r"(mtval));
+  asm volatile("csrr %0, mepc" : "=r"(mepc));
+  printf("\n FAILURE: \n mcause=0x%lx\n, mepc=0x%lx \n, mtval=0x%lx \n", mcause, mepc, mtval);
+}
+
 void _init(void)
 {
   int result;
 
   uart0_init();
 
+   // set up a bad trap handler
+  write_csr(mtvec, ((uintptr_t)&bad_trap));
+
   // set up floating point computation
   uintptr_t misa, mstatus;
   asm volatile("csrr %0, misa" : "=r"(misa));