General cleanup: remove unused signals and dead code

.github/workflows/build.yml

@@ -0,0 +1,47 @@
+name: Build Core
+
+on:
+  push:
+    branches: [main]
+  pull_request:
+    branches: [main]
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@v4
+
+      - name: Compile with Quartus
+        uses: raetro/quartus-flow@v1
+        with:
+          project: ap_core
+          version: pocket
+          project_folder: src/fpga
+
+      - name: Reverse bitstream
+        run: |
+          python3 -c "
+          with open('src/fpga/output_files/ap_core.rbf', 'rb') as f:
+              data = f.read()
+          reversed = bytes(int('{:08b}'.format(b)[::-1], 2) for b in data)
+          with open('src/fpga/output_files/bitstream.rbf_r', 'wb') as f:
+              f.write(reversed)
+          "
+
+      - name: Package core
+        run: |
+          mkdir -p release/Cores/ericlewis.LunarLander
+          cp src/fpga/output_files/bitstream.rbf_r release/Cores/ericlewis.LunarLander/
+          cp -r dist/Cores/ericlewis.LunarLander/*.json release/Cores/ericlewis.LunarLander/
+          cp dist/Cores/ericlewis.LunarLander/icon.bin release/Cores/ericlewis.LunarLander/
+          cp dist/Cores/ericlewis.LunarLander/info.txt release/Cores/ericlewis.LunarLander/
+          cp -r dist/Assets release/
+          cp -r dist/Platforms release/
+
+      - name: Upload artifact
+        uses: actions/upload-artifact@v4
+        with:
+          name: LunarLander-core
+          path: release/

src/fpga/.gitignore

@@ -25,4 +25,5 @@ cr_ie_info.json
 *.xml
 *.sld
 *.cdf
+*.cf
 

src/fpga/core/rtl/asteroids_dw.vhd

@@ -425,7 +425,7 @@ begin
   end process;
 
 
-    video_rgb : work.dpram generic map (19,4)	
+    video_rgb : entity work.dpram generic map (19,4)
 port map
 (
 	clock_a   => clk_25,

src/fpga/core/rtl/llander.vhd

@@ -103,8 +103,7 @@ architecture RTL of LLander is
   signal ena_3K               : std_ulogic;
   signal ena_12k					: std_ulogic;
   signal clk_3k					: std_ulogic;
-  signal clk_6K					: std_ulogic;
-  signal clk_12K					: std_ulogic;
+  signal clk_6k					: std_ulogic;
 
   -- cpu
   signal c_addr               : std_logic_vector(23 downto 0);
@@ -131,10 +130,8 @@ architecture RTL of LLander is
   signal dma_go_l             : std_logic;
   signal outck_l        		: std_logic;
   signal wdclr_l              : std_logic;
-  signal explode_l            : std_logic;
   signal dma_reset_l          : std_logic;
   signal audio_l              : std_logic;
-  signal noiserst_l           : std_logic;
   --
   signal shipthrusten         : std_logic;
   --
@@ -170,26 +167,16 @@ architecture RTL of LLander is
 
   signal noise_shift          : std_logic_vector(15 downto 0);
   signal noise                : std_logic;
-  signal shpsnd               : std_logic_vector(3 downto 0);
-  signal lifesnd					: std_logic_vector(3 downto 0);
 
 
-  signal lifeen					: std_logic;
   signal shpsnd_prefilter     : std_logic;
   signal shpsnd_filter_t1     : std_logic_vector(3 downto 0);
   signal shpsnd_filter_t2     : std_logic_vector(3 downto 0);
   signal shpsnd_filter_t3     : std_logic_vector(3 downto 0);
   signal shpsnd_filtered      : std_logic_vector(5 downto 0);
   signal expaud               : std_logic_vector(2 downto 0);
-  signal expitch              : std_logic_vector(1 downto 0);
-  signal noise_cnt            : std_logic_vector(3 downto 0);
-  signal expld_snd            : std_logic_vector(3 downto 0);
 
 
-  signal clkdiv2 					: std_logic_vector(3 downto 0);
-  signal audio_out2 				: std_logic_vector(7 downto 0);
-
-  signal rom_cs					: std_logic;
   signal rom_0_cs					: std_logic;
   signal rom_1_cs					: std_logic;
   signal rom_2_cs					: std_logic;
@@ -232,6 +219,7 @@ rom_v_cs <= '1' when dn_addr(13) = '1'     else '0';
     end if;
 
     clk_3k <= ena_count(10);
+    clk_6k <= ena_count(9);
   end process;
 
 
@@ -367,7 +355,6 @@ rom_v_cs <= '1' when dn_addr(13) = '1'     else '0';
 		wdclr_l    	<= decc(2);
 		dma_reset_l	<= decc(4);
 		audio_l   	<= decc(6);
-		noiserst_l 	<= decc(7);
   end process;
 
 
@@ -449,7 +436,7 @@ rom_v_cs <= '1' when dn_addr(13) = '1'     else '0';
     end case;
   end process;
 
-rom0 : work.dpram generic map (11,8)
+rom0 : entity work.dpram generic map (11,8)
 port map
 (
 	clock_a   => Clk_25,
@@ -461,7 +448,7 @@ port map
 	address_b => c_addr(10 downto 0),
 	q_b       => rom0_dout
 );	  
-rom1 : work.dpram generic map (11,8)
+rom1 : entity work.dpram generic map (11,8)
 port map
 (
 	clock_a   => Clk_25,
@@ -473,7 +460,7 @@ port map
 	address_b => c_addr(10 downto 0),
 	q_b       => rom1_dout
 );	  
-rom2 : work.dpram generic map (11,8)
+rom2 : entity work.dpram generic map (11,8)
 port map
 (
 	clock_a   => Clk_25,
@@ -485,7 +472,7 @@ port map
 	address_b => c_addr(10 downto 0),
 	q_b       => rom2_dout
 );	  
-rom3 : work.dpram generic map (11,8)
+rom3 : entity work.dpram generic map (11,8)
 port map
 (
 	clock_a   => Clk_25,
@@ -498,36 +485,6 @@ port map
 	q_b       => rom3_dout
 );	  
 
---  Internal program ROMs if the FPGA is big enough	
---  rom0 : entity work.LLANDER_PROG_ROM_0
---    port map (
---      address    	=> c_addr(10 downto 0),
---      q        	=> rom0_dout,
---      clock       => CLK_6
---      );
---
---  rom1 : entity work.LLANDER_PROG_ROM_1
---    port map (
---      address     => c_addr(10 downto 0),
---      q        	=> rom1_dout,
---      clock       => CLK_6
---      );
---
---  rom2 : entity work.LLANDER_PROG_ROM_2
---    port map (
---      address     => c_addr(10 downto 0),
---      q        	=> rom2_dout,
---      clock       => CLK_6
---      );
---
---  rom3 : entity work.LLANDER_PROG_ROM_3
---    port map (
---      address     => c_addr(10 downto 0),
---      q        	=> rom3_dout,
---      clock       => CLK_6
---      );
-
---
   p_rom_mux : process(c_addr, rom0_dout, rom1_dout, rom2_dout, rom3_dout)
   begin
     rom_dout <= (others => '0');