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Merged
bugadani merged 6 commits into from
Mar 25, 2026
Merged

C61: Add GPIO support, enable HIL test #5248

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ef97a30
C61: Add GPIO support, enable HIL test
playfulFence Mar 24, 2026
38a5698
rebase
playfulFence Mar 24, 2026
3dc8cd8
changelog entries
playfulFence Mar 24, 2026
f2d5b06
Tweak documentation
playfulFence Mar 24, 2026
d1e6a58
format gpio metadata, add ZCD analog functions
playfulFence Mar 25, 2026
38d7a93
rebase
playfulFence Mar 25, 2026
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1 change: 1 addition & 0 deletions esp-hal/CHANGELOG.md
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Expand Up @@ -51,6 +51,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Initial ESP32-C61 support (#5187, #5237)
- Add support for ADC1 on ESP32C5. (#5215)
- ESP32-C61: RNG (#5244)
- C61: Add GPIO support (#5248)

### Changed

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18 changes: 9 additions & 9 deletions esp-hal/Cargo.toml
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Expand Up @@ -104,15 +104,15 @@ ufmt-write = { version = "0.1", optional = true }
# IMPORTANT:
# Each supported device MUST have its PAC included below along with a
# corresponding feature.
esp32 = { version = "0.39", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
esp32c2 = { version = "0.28", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
esp32c3 = { version = "0.31", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
esp32c5 = { version = "0.1", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
esp32c6 = { version = "0.22", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
esp32c61 = { version = "0.1", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
esp32h2 = { version = "0.18", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
esp32s2 = { version = "0.30", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
esp32s3 = { version = "0.34", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
esp32 = { version = "0.39", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
esp32c2 = { version = "0.28", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
esp32c3 = { version = "0.31", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
esp32c5 = { version = "0.1", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
esp32c6 = { version = "0.22", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
esp32c61 = { version = "0.1", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
esp32h2 = { version = "0.18", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
esp32s2 = { version = "0.30", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
esp32s3 = { version = "0.34", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }

[target.'cfg(target_arch = "riscv32")'.dependencies]
riscv = { version = "0.15.0" }
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2 changes: 1 addition & 1 deletion esp-hal/README.md
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Expand Up @@ -72,7 +72,7 @@ For help getting started with this HAL, please refer to [The Rust on ESP Book] a
| ECC | | ⚒️ | | ⚒️ | ⚒️ | | ⚒️ | | |
| Ethernet | ❌ | | | | | | | | |
| ETM | | | | [❌][5167] [^1] | ⚒️ | | ⚒️ | | |
| GPIO | ✔️ | ✔️ | ✔️ | ⚒️ | ✔️ | | ✔️ | ✔️ | ✔️ |
| GPIO | ✔️ | ✔️ | ✔️ | ⚒️ | ✔️ | ⚒️ | ✔️ | ✔️ | ✔️ |
| HMAC | | | ⚒️ | [❌][5166] [^1] | ⚒️ | | ⚒️ | ⚒️ | ⚒️ |
| I2C master | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | | ✔️ | ✔️ | ✔️ |
| I2C slave | ❌ | | ❌ | [❌][5156] [^1] | ❌ | | ❌ | ❌ | ❌ |
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34 changes: 24 additions & 10 deletions esp-hal/src/gpio/interconnect.rs
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Expand Up @@ -53,19 +53,22 @@
//! [split](AnyPin::split) into signals. In this case you need to carefully
//! ensure that only a single driver configures the split pin, by selectively
//! [freezing](`InputSignal::freeze`) the signals.
//!
//! For example, if you want to route GPIO3 to both a Pulse Counter
//! input and a [UART](crate::uart::Uart) RX line, you will need to make sure
//! one of the signals is frozen, otherwise the driver that is configured later
//! will overwrite the other driver's configuration. Configuring the signals on
//! multiple cores is undefined behaviour unless you ensure the configuration
//! does not happen at the same time.
//!
#![cfg_attr(
uart_driver_supported,
doc = "\n\nFor example, if you want to route GPIO3 to both a Pulse Counter
input and a [UART](crate::uart::Uart) RX line, you will need to make sure
one of the signals is frozen, otherwise the driver that is configured later
will overwrite the other driver's configuration. Configuring the signals on
multiple cores is undefined behaviour unless you ensure the configuration
does not happen at the same time."
)]
//! ### Using pins and signals
//!
//! A GPIO pin can be configured either with a GPIO driver such as [`Input`], or
//! by a peripheral driver using a pin assignment method such as
//! [`Spi::with_mosi`]. The peripheral drivers' preferences can be overridden by
#![cfg_attr(spi_master_driver_supported, doc = "[`Spi::with_mosi`].")]
#![cfg_attr(not(spi_master_driver_supported), doc = "`Spi::with_mosi`.")]
//! The peripheral drivers' preferences can be overridden by
//! passing a pin driver to the peripheral driver. When converting a driver to
//! signals, the underlying signals will be initially
//! [frozen](InputSignal::freeze) to support this use case.
Expand Down Expand Up @@ -93,7 +96,10 @@
//! - A GPIO output can be driven by only one peripheral output.
//!
//! [`GPIO0`]: crate::peripherals::GPIO0
//! [`Spi::with_mosi`]: crate::spi::master::Spi::with_mosi
#![cfg_attr(
spi_master_driver_supported,
doc = "[`Spi::with_mosi`]: crate::spi::master::Spi::with_mosi"
)]

#[cfg(feature = "unstable")]
use crate::gpio::{Input, Output};
Expand Down Expand Up @@ -855,6 +861,14 @@ impl<'d> OutputSignal<'d> {

#[doc(hidden)]
#[instability::unstable]
#[cfg_attr(
not(any(
i2c_master_driver_supported,
spi_master_driver_supported,
uart_driver_supported
)),
expect(unused)
)]
pub(crate) fn connect_with_guard(self, signal: crate::gpio::OutputSignal) -> PinGuard {
signal.connect_to(&self);
match self.pin {
Expand Down
14 changes: 7 additions & 7 deletions esp-hal/src/gpio/mod.rs
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Expand Up @@ -351,7 +351,7 @@ impl TryFrom<usize> for AlternateFunction {
#[instability::unstable]
#[derive(Debug, Eq, PartialEq, Copy, Clone, Hash)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[cfg(not(any(esp32h2, esp32c5)))]
#[cfg(not(any(esp32h2, esp32c5, esp32c61)))]
pub enum RtcFunction {
/// RTC mode.
Rtc = 0,
Expand All @@ -364,7 +364,7 @@ pub enum RtcFunction {

/// Trait implemented by RTC pins
#[instability::unstable]
#[cfg(not(esp32c5))]
#[cfg(not(any(esp32c5, esp32c61)))]
pub trait RtcPin: Pin {
/// RTC number of the pin
#[cfg(any(xtensa, esp32h2))]
Expand All @@ -391,7 +391,7 @@ pub trait RtcPin: Pin {
/// Trait implemented by RTC pins which support internal pull-up / pull-down
/// resistors.
#[instability::unstable]
#[cfg(not(esp32c5))]
#[cfg(not(any(esp32c5, esp32c61)))]
pub trait RtcPinWithResistors: RtcPin {
/// Enable/disable the internal pull-up resistor
#[cfg(not(esp32h2))]
Expand Down Expand Up @@ -2202,7 +2202,7 @@ fn pin_does_not_support_function(pin: u8, function: &str) {
panic!("Pin {} is not an {}", pin, function)
}

#[cfg(not(esp32c5))]
#[cfg(not(any(esp32c5, esp32c61)))]
macro_rules! for_each_rtcio_pin {
(@impl $ident:ident, $target:ident, $gpio:ident, $code:tt) => {
if $ident.number() == $crate::peripherals::$gpio::NUMBER {
Expand All @@ -2225,7 +2225,7 @@ macro_rules! for_each_rtcio_pin {
};
}

#[cfg(not(any(esp32h2, esp32c5)))]
#[cfg(not(any(esp32h2, esp32c5, esp32c61)))]
macro_rules! for_each_rtcio_output_pin {
(@impl $ident:ident, $target:ident, $gpio:ident, $code:tt, $kind:literal) => {
if $ident.number() == $crate::peripherals::$gpio::NUMBER {
Expand Down Expand Up @@ -2257,7 +2257,7 @@ macro_rules! for_each_rtcio_output_pin {
};
}

#[cfg(not(esp32c5))]
#[cfg(not(any(esp32c5, esp32c61)))]
impl RtcPin for AnyPin<'_> {
#[cfg(any(xtensa, esp32h2))]
fn rtc_number(&self) -> u8 {
Expand Down Expand Up @@ -2287,7 +2287,7 @@ impl RtcPin for AnyPin<'_> {
}
}

#[cfg(not(esp32c5))]
#[cfg(not(any(esp32c5, esp32c61)))]
impl RtcPinWithResistors for AnyPin<'_> {
#[cfg(not(esp32h2))]
fn rtcio_pullup(&self, enable: bool) {
Expand Down
1 change: 0 additions & 1 deletion esp-hal/src/interrupt/mod.rs
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Expand Up @@ -368,7 +368,6 @@ pub(super) fn map_raw(core: Cpu, interrupt: Interrupt, cpu_interrupt: u32) {
}

/// Get cpu interrupt assigned to peripheral interrupt
#[cfg_attr(esp32c61, expect(unused))] // TODO: remove when more peripherals are supported
pub(crate) fn mapped_to(cpu: Cpu, interrupt: Interrupt) -> Option<CpuInterrupt> {
mapped_to_raw(cpu, interrupt as u32)
}
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5 changes: 4 additions & 1 deletion esp-hal/src/soc/esp32c61/mod.rs
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Expand Up @@ -15,4 +15,7 @@ pub(crate) mod regi2c;

pub(crate) use esp32c61 as pac;

pub(crate) fn pre_init() {}
pub(crate) fn pre_init() {
// this is hacky, but for some reason we must reset the output enable register manually
crate::peripherals::GPIO::regs().enable().reset();
}
6 changes: 3 additions & 3 deletions esp-lp-hal/Cargo.toml
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Expand Up @@ -45,9 +45,9 @@ nb = { version = "1.1.0", optional = true }
procmacros = { version = "0.21.0", package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }
riscv = { version = "0.15", features = ["critical-section-single-hart"] }
esp-metadata-generated = { version = "0.3.0", path = "../esp-metadata-generated" }
esp32c6-lp = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
esp32s2-ulp = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
esp32s3-ulp = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
esp32c6-lp = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
esp32s2-ulp = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
esp32s3-ulp = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }

[dev-dependencies]
panic-halt = "0.2.0"
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139 changes: 138 additions & 1 deletion esp-metadata-generated/src/_build_script_utils.rs
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Expand Up @@ -2977,6 +2977,7 @@ impl Chip {
"soc_has_ecdsa",
"soc_has_efuse",
"soc_has_etm",
"soc_has_gpio",
"soc_has_hp_apm",
"soc_has_hp_sys",
"soc_has_i2c_ana_mst",
Expand Down Expand Up @@ -3021,13 +3022,20 @@ impl Chip {
"rom_crc_le",
"rom_crc_be",
"rom_md5_bsd",
"gpio_driver_supported",
"interrupts_driver_supported",
"rng_driver_supported",
"soc_driver_supported",
"systimer_driver_supported",
"timergroup_driver_supported",
"timergroup_timg0",
"timergroup_timg1",
"gpio_gpio_function=\"1\"",
"gpio_constant_0_input=\"96\"",
"gpio_constant_1_input=\"64\"",
"gpio_func_in_sel_offset=\"0\"",
"gpio_input_signal_max=\"100\"",
"gpio_output_signal_max=\"256\"",
"interrupts_status_registers=\"3\"",
"interrupt_controller=\"clic\"",
"rng_apb_cycle_wait_num=\"16\"",
Expand Down Expand Up @@ -3074,6 +3082,7 @@ impl Chip {
"cargo:rustc-cfg=soc_has_ecdsa",
"cargo:rustc-cfg=soc_has_efuse",
"cargo:rustc-cfg=soc_has_etm",
"cargo:rustc-cfg=soc_has_gpio",
"cargo:rustc-cfg=soc_has_hp_apm",
"cargo:rustc-cfg=soc_has_hp_sys",
"cargo:rustc-cfg=soc_has_i2c_ana_mst",
Expand Down Expand Up @@ -3118,13 +3127,20 @@ impl Chip {
"cargo:rustc-cfg=rom_crc_le",
"cargo:rustc-cfg=rom_crc_be",
"cargo:rustc-cfg=rom_md5_bsd",
"cargo:rustc-cfg=gpio_driver_supported",
"cargo:rustc-cfg=interrupts_driver_supported",
"cargo:rustc-cfg=rng_driver_supported",
"cargo:rustc-cfg=soc_driver_supported",
"cargo:rustc-cfg=systimer_driver_supported",
"cargo:rustc-cfg=timergroup_driver_supported",
"cargo:rustc-cfg=timergroup_timg0",
"cargo:rustc-cfg=timergroup_timg1",
"cargo:rustc-cfg=gpio_gpio_function=\"1\"",
"cargo:rustc-cfg=gpio_constant_0_input=\"96\"",
"cargo:rustc-cfg=gpio_constant_1_input=\"64\"",
"cargo:rustc-cfg=gpio_func_in_sel_offset=\"0\"",
"cargo:rustc-cfg=gpio_input_signal_max=\"100\"",
"cargo:rustc-cfg=gpio_output_signal_max=\"256\"",
"cargo:rustc-cfg=interrupts_status_registers=\"3\"",
"cargo:rustc-cfg=interrupt_controller=\"clic\"",
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
Expand Down Expand Up @@ -3176,7 +3192,128 @@ impl Chip {
),
],
},
pins: &[],
pins: &[
PinInfo {
pin: 0,
limitations: &[],
},
PinInfo {
pin: 1,
limitations: &[],
},
PinInfo {
pin: 2,
limitations: &[],
},
PinInfo {
pin: 3,
limitations: &["strapping", "jtag"],
},
PinInfo {
pin: 4,
limitations: &["strapping", "jtag"],
},
PinInfo {
pin: 5,
limitations: &["jtag"],
},
PinInfo {
pin: 6,
limitations: &["jtag"],
},
PinInfo {
pin: 7,
limitations: &["strapping"],
},
PinInfo {
pin: 8,
limitations: &["strapping"],
},
PinInfo {
pin: 9,
limitations: &["strapping"],
},
PinInfo {
pin: 10,
limitations: &["bootloader_uart"],
},
PinInfo {
pin: 11,
limitations: &["bootloader_uart"],
},
PinInfo {
pin: 12,
limitations: &["usb_jtag"],
},
PinInfo {
pin: 13,
limitations: &["usb_jtag"],
},
PinInfo {
pin: 14,
limitations: &["spi_flash"],
},
PinInfo {
pin: 15,
limitations: &["spi_flash"],
},
PinInfo {
pin: 16,
limitations: &["spi_flash"],
},
PinInfo {
pin: 17,
limitations: &["spi_flash"],
},
PinInfo {
pin: 18,
limitations: &["spi_flash"],
},
PinInfo {
pin: 19,
limitations: &["spi_flash"],
},
PinInfo {
pin: 20,
limitations: &["spi_flash"],
},
PinInfo {
pin: 21,
limitations: &["spi_flash"],
},
PinInfo {
pin: 22,
limitations: &[],
},
PinInfo {
pin: 23,
limitations: &[],
},
PinInfo {
pin: 24,
limitations: &[],
},
PinInfo {
pin: 25,
limitations: &[],
},
PinInfo {
pin: 26,
limitations: &[],
},
PinInfo {
pin: 27,
limitations: &[],
},
PinInfo {
pin: 28,
limitations: &[],
},
PinInfo {
pin: 29,
limitations: &[],
},
],
},
Self::Esp32h2 => Config {
architecture: "riscv",
Expand Down
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