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suda-morrissuda-morris
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Merge branch 'feature/esp32c5_eco2_gpio_update' into 'master'
feat(gpio): esp32c5 eco2 gpio update Closes IDF-12653, IDF-12710, and IO22-24 See merge request espressif/esp-idf!38358
2 parents 186f2a8 + 6994be3 commit a4d32bb

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24 files changed

+4842
-6583
lines changed

24 files changed

+4842
-6583
lines changed

‎components/esp_driver_gpio/src/gpio.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,7 @@ static gpio_context_t gpio_context = {
7575

7676
esp_err_t gpio_pullup_en(gpio_num_t gpio_num)
7777
{
78-
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
78+
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error (input-only pad has no internal PU)", ESP_ERR_INVALID_ARG);
7979

8080
if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
8181
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
@@ -113,7 +113,7 @@ esp_err_t gpio_pullup_dis(gpio_num_t gpio_num)
113113

114114
esp_err_t gpio_pulldown_en(gpio_num_t gpio_num)
115115
{
116-
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
116+
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error (input-only pad has no internal PD)", ESP_ERR_INVALID_ARG);
117117

118118
if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
119119
portENTER_CRITICAL(&gpio_context.gpio_spinlock);

‎components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -96,7 +96,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
9696
GPIO_NUM_21, //GPIO21
9797
};
9898
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO6
99-
#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5
99+
#elif CONFIG_IDF_TARGET_ESP32C6
100100
// Has no input-only rtcio pins, all pins support pull-up/down
101101
#define RTCIO_SUPPORT_PU_PD(num) 1
102102
#define TEST_GPIO_PIN_COUNT 8
@@ -146,7 +146,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
146146
GPIO_NUM_14, //GPIO14
147147
GPIO_NUM_15, //GPIO15
148148
};
149-
#elif CONFIG_IDF_TARGET_ESP32C61
149+
#elif CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C5
150150
// Has no input-only rtcio pins, all pins support pull-up/down
151151
#define RTCIO_SUPPORT_PU_PD(num) 1
152152
#define TEST_GPIO_PIN_COUNT 7

‎components/hal/esp32c5/include/hal/i2c_ll.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -82,11 +82,11 @@ typedef enum {
8282

8383
// Record for Pins usage logs
8484

85-
#define LP_I2C_SCL_PIN_ERR_LOG "SCL pin can only be configured as GPIO#7"
86-
#define LP_I2C_SDA_PIN_ERR_LOG "SDA pin can only be configured as GPIO#6"
85+
#define LP_I2C_SCL_PIN_ERR_LOG "SCL pin can only be configured as GPIO#3"
86+
#define LP_I2C_SDA_PIN_ERR_LOG "SDA pin can only be configured as GPIO#2"
8787

88-
#define LP_I2C_SDA_IOMUX_PAD 6
89-
#define LP_I2C_SCL_IOMUX_PAD 7
88+
#define LP_I2C_SDA_IOMUX_PAD 2
89+
#define LP_I2C_SCL_IOMUX_PAD 3
9090

9191
/**
9292
* @brief Calculate I2C bus frequency

‎components/hal/esp32c5/include/hal/rtc_io_ll.h‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
101101
*/
102102
static inline void rtcio_ll_output_enable(int rtcio_num)
103103
{
104-
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, out_enable_w1ts, BIT(rtcio_num));
104+
LP_GPIO.enable_w1ts.enable_w1ts = BIT(rtcio_num);
105105
}
106106

107107
/**
@@ -111,7 +111,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
111111
*/
112112
static inline void rtcio_ll_output_disable(int rtcio_num)
113113
{
114-
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1tc, out_enable_w1tc, BIT(rtcio_num));
114+
LP_GPIO.enable_w1tc.enable_w1tc = BIT(rtcio_num);
115115
}
116116

117117
/**
@@ -123,9 +123,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
123123
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
124124
{
125125
if (level) {
126-
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1ts, out_data_w1ts, BIT(rtcio_num));
126+
LP_GPIO.out_w1ts.out_w1ts = BIT(rtcio_num);
127127
} else {
128-
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1tc, out_data_w1tc, BIT(rtcio_num));
128+
LP_GPIO.out_w1tc.out_w1tc = BIT(rtcio_num);
129129
}
130130
}
131131

@@ -157,7 +157,7 @@ static inline void rtcio_ll_input_disable(int rtcio_num)
157157
*/
158158
static inline uint32_t rtcio_ll_get_level(int rtcio_num)
159159
{
160-
return (uint32_t)(HAL_FORCE_READ_U32_REG_FIELD(LP_GPIO.in, in_data_next) >> rtcio_num) & 0x1;
160+
return (LP_GPIO.in.in_data_next >> rtcio_num) & 0x1;
161161
}
162162

163163
/**
@@ -428,15 +428,15 @@ static inline bool rtcio_ll_wakeup_is_enabled(int rtcio_num)
428428
*/
429429
static inline uint32_t rtcio_ll_get_interrupt_status(void)
430430
{
431-
return (uint32_t)HAL_FORCE_READ_U32_REG_FIELD(LP_GPIO.status, status_interrupt);
431+
return LP_GPIO.status.status_interrupt;
432432
}
433433

434434
/**
435435
* @brief Clear all LP IO pads status
436436
*/
437437
static inline void rtcio_ll_clear_interrupt_status(void)
438438
{
439-
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.status_w1tc, status_intr_w1tc, 0xff);
439+
LP_GPIO.status_w1tc.status_w1tc = 0x7F;
440440
}
441441

442442
#ifdef __cplusplus

‎components/soc/esp32c5/i2c_periph.c‎

Lines changed: 3 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,21 +1,13 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

77
#include "soc/i2c_periph.h"
88
#include "soc/gpio_sig_map.h"
99

10-
/*
11-
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
12-
*/
13-
typedef enum {
14-
LP_I2C_MUX_FUNC = 0,
15-
LP_GPIO_MUX_FUNC = 1,
16-
LP_IO_MUX_FUNC_NUM = 2,
17-
LP_MUX_FUNC_NOT_USED = 0xFF,
18-
} lp_io_mux_func_t;
10+
#define LP_I2C_MUX_FUNC (3)
1911

2012
static_assert(SOC_I2C_NUM == (SOC_HP_I2C_NUM + SOC_LP_I2C_NUM));
2113

@@ -26,7 +18,6 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
2618
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
2719
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
2820
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
29-
.iomux_func = (uint8_t)LP_MUX_FUNC_NOT_USED,
3021
.irq = ETS_I2C_EXT0_INTR_SOURCE,
3122
},
3223
/* LP_I2C_NUM_0*/
@@ -35,7 +26,7 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
3526
.sda_in_sig = 0,
3627
.scl_out_sig = 0,
3728
.scl_in_sig = 0,
38-
.iomux_func = (uint8_t)LP_I2C_MUX_FUNC,
29+
.iomux_func = LP_I2C_MUX_FUNC,
3930
.irq = ETS_LP_I2C_INTR_SOURCE,
4031
},
4132
};

‎components/soc/esp32c5/include/soc/Kconfig.soc_caps.in‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -541,11 +541,11 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
541541

542542
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
543543
int
544-
default 8
544+
default 7
545545

546546
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
547547
hex
548-
default 0x0000000001FFFF00
548+
default 0x0000000001FFFF80
549549

550550
config SOC_GPIO_SUPPORT_FORCE_HOLD
551551
bool
@@ -565,7 +565,7 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
565565

566566
config SOC_RTCIO_PIN_COUNT
567567
int
568-
default 8
568+
default 7
569569

570570
config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
571571
bool

‎components/soc/esp32c5/include/soc/rtc_io_channel.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,3 @@
2626

2727
#define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6
2828
#define RTCIO_CHANNEL_6_GPIO_NUM 6
29-
30-
#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7
31-
#define RTCIO_CHANNEL_7_GPIO_NUM 7

‎components/soc/esp32c5/include/soc/soc_caps.h‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -223,11 +223,11 @@
223223
#define SOC_GPIO_IN_RANGE_MAX 28
224224
#define SOC_GPIO_OUT_RANGE_MAX 28
225225

226-
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
227-
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (8)
226+
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
227+
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7)
228228

229-
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_28)
230-
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF00ULL
229+
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_28)
230+
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF80ULL
231231

232232
// Support to force hold all IOs
233233
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
@@ -241,7 +241,7 @@
241241
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
242242

243243
/*-------------------------- RTCIO CAPS --------------------------------------*/
244-
#define SOC_RTCIO_PIN_COUNT 8
244+
#define SOC_RTCIO_PIN_COUNT 7
245245
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,
246246
* so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
247247
* when the pins are switched to RTC function.

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