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Hardware versions

Florian edited this page Jan 4, 2017 · 8 revisions

On this page all created hardware versions are listed. For each version there is a unique ID, which was created with the qsys sysid creator and can be accessed by software. The sysid is available as well from NIOS2 as from the HPS.
For every version listed here there is a folder within /FPGA_Design/output_files which contains the *.sof and *.sopcinfo files for flashing and programming for the NIOS2. It is not necessary that there is for each hardware version described here a git-tag/github-release.

Overview

All versions starting with 0 (e.g 0.1) contains at least the following components:

  • HPS (ARM A9) subsystem with memory
    • connected pushbuttons for
      • cold reset
      • warm reset
      • debug reset
    • a led (hardware connection directly from HPS-GPIO, no fpga used)
  • FPGA subsystem containing
    • NIOS 2 with
      • onchip memory with 128kB RAM
      • JTAG-UART bridge for debug output messages via the jtag chain
    • Onboard LED as PIO components
    • Onboard dipswitchs as PIO components
    • Onboard pushbuttons as PIO components
    • a system timer which generates a tick every 1 ms

Versions

Version Description related git version HW SysId output files folder
0.1 This is the initial version. It contains all components described in @Overivew. SHA 25fc800d 0x01112016 /01112016
0.2 Contains all components from V0.1 plus some peripheral and a faster clock SHA a3f4dc95 0x13112016 /13112016
0.21 like version V0.2, but build with Quartus license -> there is additional a flashable file *.jic within the folder SHA 64c0c80e 0x13112016 /13112016_f
0.3 like version V0.2, but added PWM and rotary encoder SHA 84910e8 0x06012017 /06012017

Detail Description

V0.1

  • a time limited sof file
  • witout a sysid accessable from the HPS
  • NIOS 2 f version (fast implementation, needs a license -> time limited)
  • system timer with 1 ms tick
  • HPS and FPGA are connected via one 50 MHz clock, this will change in later versions HardwareComponents_V0.1_png

V0.2

  • all features from version V0.1
  • additional one I2C and one SPI with 3 chipselects (only 2 are physical connected)
  • the IOs for the lighting of the car are added
  • 8 GPIOs for generic use are added. Only one is physical connected will be used for Data/Command switch of the tft. HardwareComponents_V0.2_png

V0.3

  • all features from version V0.2
  • added a rotary encoder IP Core
  • added a pwm IP Core with two instances (for motor and steering)

All concret phyiscal connections are documented in the schematics.

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