simd: riscv: implement RVV intrinsics #9731

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged

edsiper merged 9 commits into master from cosmo0920-implement-rvv-intrinsics

Mar 29, 2025

Merged

simd: riscv: implement RVV intrinsics #9731

simd: Untabify for highbit set instruction

GitHub Actions / hadolint succeeded Jan 20, 2025 in 0s

reviewdog [hadolint] report

reported by reviewdog 🐶

Findings (0)

Filtered Findings (0)

View more details on GitHub Actions