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Address review comments
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4 files changed

+23
-31
lines changed

4 files changed

+23
-31
lines changed

clang/include/clang/CIR/Dialect/IR/CIROps.td

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1729,7 +1729,7 @@ def SetBitfieldOp : CIR_Op<"set_bitfield"> {
17291729
Arg<CIR_PointerType, "the address to store the value", [MemWrite]>:$addr,
17301730
CIR_AnyType:$src,
17311731
BitfieldInfoAttr:$bitfield_info,
1732-
OptionalAttr<I64Attr>:$alignment,
1732+
DefaultValuedOptionalAttr<I64Attr, "0">:$alignment,
17331733
UnitAttr:$is_volatile
17341734
);
17351735

@@ -1757,10 +1757,7 @@ def SetBitfieldOp : CIR_Op<"set_bitfield"> {
17571757
BitfieldInfoAttr::get($_builder.getContext(),
17581758
name, storage_type,
17591759
size, offset, is_signed);
1760-
build($_builder, $_state, type, addr, src, info,
1761-
alignment == 0 ? IntegerAttr()
1762-
: $_builder.getI64IntegerAttr(alignment),
1763-
is_volatile);
1760+
build($_builder, $_state, type, addr, src, info, alignment, is_volatile);
17641761
}]>
17651762
];
17661763
}
@@ -1819,7 +1816,7 @@ def GetBitfieldOp : CIR_Op<"get_bitfield"> {
18191816
let arguments = (ins
18201817
Arg<CIR_PointerType, "the address to load from", [MemRead]>:$addr,
18211818
BitfieldInfoAttr:$bitfield_info,
1822-
OptionalAttr<I64Attr>:$alignment,
1819+
DefaultValuedOptionalAttr<I64Attr, "0">:$alignment,
18231820
UnitAttr:$is_volatile
18241821
);
18251822

@@ -1846,10 +1843,7 @@ def GetBitfieldOp : CIR_Op<"get_bitfield"> {
18461843
BitfieldInfoAttr::get($_builder.getContext(),
18471844
name, storage_type,
18481845
size, offset, is_signed);
1849-
build($_builder, $_state, type, addr, info,
1850-
alignment == 0 ? IntegerAttr()
1851-
: $_builder.getI64IntegerAttr(alignment),
1852-
is_volatile);
1846+
build($_builder, $_state, type, addr, info, alignment, is_volatile);
18531847
}]>
18541848
];
18551849
}

clang/lib/CIR/CodeGen/CIRGenBuilder.h

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -424,23 +424,23 @@ class CIRGenBuilderTy : public cir::CIRBaseBuilderTy {
424424
}
425425

426426
mlir::Value createSetBitfield(mlir::Location loc, mlir::Type resultType,
427-
mlir::Value dstAddr, mlir::Type storageType,
427+
Address dstAddr, mlir::Type storageType,
428428
mlir::Value src, const CIRGenBitFieldInfo &info,
429-
bool isLvalueVolatile, bool useVolatile,
430-
unsigned alignment = 0) {
429+
bool isLvalueVolatile, bool useVolatile) {
431430
return create<cir::SetBitfieldOp>(
432-
loc, resultType, dstAddr, storageType, src, info.name, info.size,
433-
info.offset, info.isSigned, isLvalueVolatile, alignment);
431+
loc, resultType, dstAddr.getPointer(), storageType, src, info.name,
432+
info.size, info.offset, info.isSigned, isLvalueVolatile,
433+
dstAddr.getAlignment().getAsAlign().value());
434434
}
435435

436436
mlir::Value createGetBitfield(mlir::Location loc, mlir::Type resultType,
437-
mlir::Value addr, mlir::Type storageType,
437+
Address addr, mlir::Type storageType,
438438
const CIRGenBitFieldInfo &info,
439-
bool isLvalueVolatile, bool useVolatile,
440-
unsigned alignment = 0) {
439+
bool isLvalueVolatile, bool useVolatile) {
441440
return create<cir::GetBitfieldOp>(
442-
loc, resultType, addr, storageType, info.name, info.size, info.offset,
443-
info.isSigned, isLvalueVolatile, alignment);
441+
loc, resultType, addr.getPointer(), storageType, info.name, info.size,
442+
info.offset, info.isSigned, isLvalueVolatile,
443+
addr.getAlignment().getAsAlign().value());
444444
}
445445
};
446446

clang/lib/CIR/CodeGen/CIRGenExpr.cpp

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -337,10 +337,9 @@ mlir::Value CIRGenFunction::emitStoreThroughBitfieldLValue(RValue src,
337337

338338
mlir::Value dstAddr = dst.getAddress().getPointer();
339339

340-
return builder.createSetBitfield(
341-
dstAddr.getLoc(), resLTy, dstAddr, ptr.getElementType(), src.getValue(),
342-
info, dst.isVolatileQualified(), useVolatile,
343-
dst.getAddress().getAlignment().getAsAlign().value());
340+
return builder.createSetBitfield(dstAddr.getLoc(), resLTy, ptr,
341+
ptr.getElementType(), src.getValue(), info,
342+
dst.isVolatileQualified(), useVolatile);
344343
}
345344

346345
RValue CIRGenFunction::emitLoadOfBitfieldLValue(LValue lv, SourceLocation loc) {
@@ -352,9 +351,9 @@ RValue CIRGenFunction::emitLoadOfBitfieldLValue(LValue lv, SourceLocation loc) {
352351

353352
assert(!cir::MissingFeatures::armComputeVolatileBitfields());
354353

355-
mlir::Value field = builder.createGetBitfield(
356-
getLoc(loc), resLTy, ptr.getPointer(), ptr.getElementType(), info,
357-
lv.isVolatile(), false, ptr.getAlignment().getAsAlign().value());
354+
mlir::Value field =
355+
builder.createGetBitfield(getLoc(loc), resLTy, ptr, ptr.getElementType(),
356+
info, lv.isVolatile(), false);
358357
assert(!cir::MissingFeatures::opLoadEmitScalarRangeCheck() && "NYI");
359358
return RValue::get(field);
360359
}

clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2555,7 +2555,7 @@ mlir::LogicalResult CIRToLLVMSetBitfieldOpLowering::matchAndRewrite(
25552555
assert(storageSize > size && "Invalid bitfield size.");
25562556

25572557
mlir::Value val = rewriter.create<mlir::LLVM::LoadOp>(
2558-
op.getLoc(), intType, adaptor.getAddr(), op.getAlignment().value(),
2558+
op.getLoc(), intType, adaptor.getAddr(), op.getAlignment(),
25592559
op.getIsVolatile());
25602560

25612561
srcVal =
@@ -2572,8 +2572,7 @@ mlir::LogicalResult CIRToLLVMSetBitfieldOpLowering::matchAndRewrite(
25722572
}
25732573

25742574
rewriter.create<mlir::LLVM::StoreOp>(op.getLoc(), srcVal, adaptor.getAddr(),
2575-
op.getAlignment().value(),
2576-
op.getIsVolatile());
2575+
op.getAlignment(), op.getIsVolatile());
25772576

25782577
mlir::Type resultTy = getTypeConverter()->convertType(op.getType());
25792578

@@ -2647,7 +2646,7 @@ mlir::LogicalResult CIRToLLVMGetBitfieldOpLowering::matchAndRewrite(
26472646
computeBitfieldIntType(storageType, context, storageSize);
26482647

26492648
mlir::Value val = rewriter.create<mlir::LLVM::LoadOp>(
2650-
op.getLoc(), intType, adaptor.getAddr(), op.getAlignment().value(),
2649+
op.getLoc(), intType, adaptor.getAddr(), op.getAlignment(),
26512650
op.getIsVolatile());
26522651
val = rewriter.create<mlir::LLVM::BitcastOp>(op.getLoc(), intType, val);
26532652

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