[RISCV] Add missing assembler test case for c.addi zero, 0. NFC

[topperc]

This is an assembly only alias for c.nop.

[llvmbot]

@llvm/pr-subscribers-mc

Author: Craig Topper (topperc)

Changes

This is an assembly only alias for c.nop.

---

Full diff: https://github.com/llvm/llvm-project/pull/112291.diff

1 Files Affected:

• (modified) llvm/test/MC/RISCV/rv32c-valid.s (+5)

diff --git a/llvm/test/MC/RISCV/rv32c-valid.s b/llvm/test/MC/RISCV/rv32c-valid.s
index c9e9b0053173be..bcdf27a2ba783b 100644
--- a/llvm/test/MC/RISCV/rv32c-valid.s
+++ b/llvm/test/MC/RISCV/rv32c-valid.s
@@ -147,6 +147,11 @@ c.sub a4, a5
 # CHECK-ASM: encoding: [0x01,0x00]
 # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
 c.nop
+# CHECK-ASM: c.addi zero, 0
+# CHECK-OBJ: c.nop
+# CHECK-ASM: encoding: [0x01,0x00]
+# CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
+c.addi x0, 0
 # CHECK-ASM-AND-OBJ: c.ebreak
 # CHECK-ASM: encoding: [0x02,0x90]
 # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}

[dtcxzyw]

The spec says "C.ADDI is only valid when rd≠x0 and imm≠0".

[topperc]

I know, but this syntax is supported by binutils. We have internal tests from our hardware validation team that uses this syntax.

The isa-manual used to say "C.NOP is encoded as c.addi x0, 0 and so expands to addi x0, x0, 0. Breakpoint Instruction." but it was changed 6 years ago. riscv/riscv-isa-manual#248

[dtcxzyw]

I know, but this syntax is supported by binutils.

Make sense to me.

[dtcxzyw]

LG