[ARM] Fix warnings in ARMAsmParser.cpp and ARMDisassembler.cpp #112507
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Fix gcc warnings like: ARMAsmParser.cpp:7168:46: warning: enumeral and non-enumeral type in conditional expression [-Wextra]
Member
|
@llvm/pr-subscribers-backend-arm Author: Karl-Johan Karlsson (karka228) ChangesFix gcc warnings like: Full diff: https://github.com/llvm/llvm-project/pull/112507.diff 2 Files Affected:
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 75fb90477f8854..0623a973dfd075 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -2532,14 +2532,14 @@ class ARMOperand : public MCParsedAsmOperand {
void addCondCodeOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
- unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
+ unsigned RegNum = getCondCode() == ARMCC::AL ? 0: (unsigned)ARM::CPSR;
Inst.addOperand(MCOperand::createReg(RegNum));
}
void addVPTPredNOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
- unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0;
+ unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: (unsigned)ARM::P0;
Inst.addOperand(MCOperand::createReg(RegNum));
Inst.addOperand(MCOperand::createReg(0));
}
@@ -7165,7 +7165,7 @@ bool ARMAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
if (CanAcceptCarrySet && CarrySetting) {
SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
Operands.push_back(
- ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, Loc, *this));
+ ARMOperand::CreateCCOut(CarrySetting ? (unsigned)ARM::CPSR : 0, Loc, *this));
}
// Add the predication code operand, if necessary.
@@ -10372,7 +10372,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
case ARM::t2ASRri:
if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
isARMLowRegister(Inst.getOperand(1).getReg()) &&
- Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
+ Inst.getOperand(5).getReg() == (inITBlock() ? 0 : (unsigned)ARM::CPSR) &&
!HasWideQualifier) {
unsigned NewOpc;
switch (Inst.getOpcode()) {
@@ -10422,14 +10422,14 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
TmpInst.addOperand(Inst.getOperand(0)); // Rd
if (isNarrow)
TmpInst.addOperand(MCOperand::createReg(
- Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
+ Inst.getOpcode() == ARM::t2MOVSsr ? (unsigned)ARM::CPSR : 0));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // Rm
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
if (!isNarrow)
TmpInst.addOperand(MCOperand::createReg(
- Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
+ Inst.getOpcode() == ARM::t2MOVSsr ? (unsigned)ARM::CPSR : 0));
Inst = TmpInst;
return true;
}
@@ -10475,7 +10475,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
TmpInst.addOperand(Inst.getOperand(0)); // Rd
if (isNarrow && !isMov)
TmpInst.addOperand(MCOperand::createReg(
- Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
+ Inst.getOpcode() == ARM::t2MOVSsi ? (unsigned)ARM::CPSR : 0));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
if (newOpc != ARM::t2RRX && !isMov)
TmpInst.addOperand(MCOperand::createImm(Amount));
@@ -10483,7 +10483,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
TmpInst.addOperand(Inst.getOperand(4));
if (!isNarrow)
TmpInst.addOperand(MCOperand::createReg(
- Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
+ Inst.getOpcode() == ARM::t2MOVSsi ? (unsigned)ARM::CPSR : 0));
Inst = TmpInst;
return true;
}
@@ -10684,7 +10684,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
!isARMLowRegister(Inst.getOperand(0).getReg()) ||
(Inst.getOperand(2).isImm() &&
(unsigned)Inst.getOperand(2).getImm() > 255) ||
- Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) ||
+ Inst.getOperand(5).getReg() != (inITBlock() ? 0 : (unsigned)ARM::CPSR) ||
HasWideQualifier)
break;
MCInst TmpInst;
@@ -10852,7 +10852,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
(Inst.getOperand(1).isImm() &&
(unsigned)Inst.getOperand(1).getImm() <= 255) &&
- Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
+ Inst.getOperand(4).getReg() == (inITBlock() ? 0 : (unsigned)ARM::CPSR) &&
!HasWideQualifier) {
// The operands aren't in the same order for tMOVi8...
MCInst TmpInst;
@@ -10993,7 +10993,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
isARMLowRegister(Inst.getOperand(2).getReg())) &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
- Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
+ Inst.getOperand(5).getReg() == (inITBlock() ? 0 : (unsigned)ARM::CPSR) &&
!HasWideQualifier) {
unsigned NewOpc;
switch (Inst.getOpcode()) {
@@ -11029,7 +11029,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
isARMLowRegister(Inst.getOperand(2).getReg())) &&
(Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
- Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
+ Inst.getOperand(5).getReg() == (inITBlock() ? 0 : (unsigned)ARM::CPSR) &&
!HasWideQualifier) {
unsigned NewOpc;
switch (Inst.getOpcode()) {
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 93b74905fc59fc..8c348c07aeacff 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -894,12 +894,12 @@ void ARMDisassembler::AddThumb1SBit(MCInst &MI, bool InITBlock) const {
MCID.operands()[i].RegClass == ARM::CCRRegClassID) {
if (i > 0 && MCID.operands()[i - 1].isPredicate())
continue;
- MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(InITBlock ? 0 : (unsigned)ARM::CPSR));
return;
}
}
- MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(InITBlock ? 0 : (unsigned)ARM::CPSR));
}
bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const {
|
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
davemgreen
reviewed
Oct 16, 2024
Collaborator
davemgreen
left a comment
davemgreen
left a comment
There was a problem hiding this comment.
I had a patch to address this, I was sitting on it for a while whilst it was in the queue of commits. I think this should be using ARM::NoRegister instead of 0, which should fix the warning too without the need for the cast.
Collaborator
Author
That sounds fine. Do you want to bring back your patch to address this or should I change my patch to use ARM::NoRegister? |
Use ARM::NoRegister instead of 0.
davemgreen
approved these changes
Oct 16, 2024
Collaborator
davemgreen
left a comment
davemgreen
left a comment
There was a problem hiding this comment.
No this sounds great. Let's do this here. Thanks for doing it.
LGTM.
davemgreen
added a commit
that referenced
this pull request
Oct 18, 2024
Similar to #112507, this uses ARM::NoRegister in a few more places, as opposed to the constant 0.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
3 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Fix gcc warnings like:
ARMAsmParser.cpp:7168:46: warning: enumeral and non-enumeral type in conditional expression [-Wextra]