Skip to content

[RISCV] Add OperandType for sew and vecpolicy operands. #114168

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Oct 30, 2024
Merged

[RISCV] Add OperandType for sew and vecpolicy operands. #114168

Show file tree
Hide file tree
Changes from 2 commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
b5303f6
[RISCV] Add OperandType for sew and vecpolicy operands.
topperc Oct 30, 2024
dcbb655
fixup! rename vecpolicy -> vec_policy.
topperc Oct 30, 2024
9948a6e
Merge remote-tracking branch 'origin/main' into pr/sew-vecpolicy
topperc Oct 30, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 5 additions & 1 deletion llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -335,7 +335,11 @@ enum OperandType : unsigned {
OPERAND_FRMARG,
// Operand is a 3-bit rounding mode where only RTZ is valid.
OPERAND_RTZARG,
OPERAND_LAST_RISCV_IMM = OPERAND_RTZARG,
// Vector policy operand.
OPERAND_VEC_POLICY,
// Vector SEW operand.
OPERAND_SEW,
OPERAND_LAST_RISCV_IMM = OPERAND_SEW,
// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli
// or vsetivli.
Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2542,6 +2542,12 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_RTZARG:
Ok = Imm == RISCVFPRndMode::RTZ;
break;
case RISCVOp::OPERAND_VEC_POLICY:
Ok = (Imm & (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC)) == Imm;
Copy link
Member

@dtcxzyw dtcxzyw Oct 30, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Can be simplified to Imm <= (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC).

Copy link
Member

@dtcxzyw dtcxzyw Oct 30, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Oops, it is a signed integer :(

break;
case RISCVOp::OPERAND_SEW:
Ok = Imm == 0 || (Imm >= 3 && Imm <= 6);
break;
}
if (!Ok) {
ErrInfo = "Invalid immediate";
Expand Down
Loading
Loading