[RISCV] Add OperandType for vector rounding mode operands. #114179
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesUse TSFlags to distinquish which type of rounding mode it is. Patch is 34.75 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/114179.diff 6 Files Affected:
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index d3899425ff843d..19103e219cb800 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -337,7 +337,13 @@ enum OperandType : unsigned {
OPERAND_RTZARG,
// Condition code used by select and short forward branch pseudos.
OPERAND_COND_CODE,
- OPERAND_LAST_RISCV_IMM = OPERAND_COND_CODE,
+ // Vector policy operand.
+ OPERAND_VEC_POLICY,
+ // Vector SEW operand.
+ OPERAND_SEW,
+ // Vector rounding mode for VXRM or FRM.
+ OPERAND_VEC_RM,
+ OPERAND_LAST_RISCV_IMM = OPERAND_VEC_RM,
// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli
// or vsetivli.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 0cfe4eb063485f..688da1ee1b33fb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2545,6 +2545,19 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_COND_CODE:
Ok = Imm >= 0 && Imm < RISCVCC::COND_INVALID;
break;
+ case RISCVOp::OPERAND_VEC_POLICY:
+ Ok = (Imm & (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC)) == Imm;
+ break;
+ case RISCVOp::OPERAND_SEW:
+ Ok = Imm == 0 || (Imm >= 3 && Imm <= 6);
+ break;
+ case RISCVOp::OPERAND_VEC_RM:
+ assert(RISCVII::hasRoundModeOp(Desc.TSFlags));
+ if (RISCVII::usesVXRM(Desc.TSFlags))
+ Ok = isUInt<2>(Imm);
+ else
+ Ok = RISCVFPRndMode::isValidRoundingMode(Imm);
+ break;
}
if (!Ok) {
ErrInfo = "Invalid immediate";
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index af4f653f57afd5..1d44037e81d99b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -84,6 +84,18 @@ def AVL : RegisterOperand<GPRNoX0> {
let OperandType = "OPERAND_AVL";
}
+def vec_policy : RISCVOp {
+ let OperandType = "OPERAND_VEC_POLICY";
+}
+
+def sew : RISCVOp {
+ let OperandType = "OPERAND_SEW";
+}
+
+def vec_rm : RISCVOp {
+ let OperandType = "OPERAND_VEC_RM";
+}
+
// X0 has special meaning for vsetvl/vsetvli.
// rd | rs1 | AVL value | Effect on vl
//--------------------------------------------------------------
@@ -764,8 +776,8 @@ class GetVTypePredicates<VTypeInfo vti> {
class VPseudoUSLoadNoMask<VReg RetClass,
int EEW> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew,
- ixlenimm:$policy), []>,
+ (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sew:$sew,
+ vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -782,7 +794,7 @@ class VPseudoUSLoadMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMem:$rs1,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -799,7 +811,7 @@ class VPseudoUSLoadFFNoMask<VReg RetClass,
int EEW> :
Pseudo<(outs RetClass:$rd, GPR:$vl),
(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
- ixlenimm:$sew, ixlenimm:$policy), []>,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -816,7 +828,7 @@ class VPseudoUSLoadFFMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMem:$rs1,
- VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -833,7 +845,7 @@ class VPseudoSLoadNoMask<VReg RetClass,
int EEW> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl,
- ixlenimm:$sew, ixlenimm:$policy), []>,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -850,7 +862,7 @@ class VPseudoSLoadMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMem:$rs1, GPR:$rs2,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -872,7 +884,7 @@ class VPseudoILoadNoMask<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
- ixlenimm:$sew, ixlenimm:$policy), []>,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
@@ -895,7 +907,7 @@ class VPseudoILoadMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMem:$rs1, IdxClass:$rs2,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
@@ -912,7 +924,7 @@ class VPseudoILoadMask<VReg RetClass,
class VPseudoUSStoreNoMask<VReg StClass,
int EEW> :
Pseudo<(outs),
- (ins StClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew), []>,
+ (ins StClass:$rd, GPRMem:$rs1, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
@@ -926,7 +938,7 @@ class VPseudoUSStoreMask<VReg StClass,
int EEW> :
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSE</*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
@@ -940,7 +952,7 @@ class VPseudoSStoreNoMask<VReg StClass,
int EEW> :
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, GPR:$rs2,
- AVL:$vl, ixlenimm:$sew), []>,
+ AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSE</*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
let mayLoad = 0;
@@ -954,7 +966,7 @@ class VPseudoSStoreMask<VReg StClass,
int EEW> :
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, GPR:$rs2,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSE</*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
let mayLoad = 0;
@@ -967,7 +979,7 @@ class VPseudoSStoreMask<VReg StClass,
class VPseudoNullaryNoMask<VReg RegClass> :
Pseudo<(outs RegClass:$rd),
(ins RegClass:$passthru,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -981,7 +993,7 @@ class VPseudoNullaryNoMask<VReg RegClass> :
class VPseudoNullaryMask<VReg RegClass> :
Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
(ins GetVRegNoV0<RegClass>.R:$passthru,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -996,7 +1008,7 @@ class VPseudoNullaryMask<VReg RegClass> :
// Nullary for pseudo instructions. They are expanded in
// RISCVExpandPseudoInsts pass.
class VPseudoNullaryPseudoM<string BaseInst> :
- Pseudo<(outs VR:$rd), (ins AVL:$vl, ixlenimm:$sew), []>,
+ Pseudo<(outs VR:$rd), (ins AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1016,7 +1028,7 @@ class VPseudoUnaryNoMask<DAGOperand RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, OpClass:$rs2,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1033,7 +1045,7 @@ class VPseudoUnaryNoMaskNoPolicy<DAGOperand RetClass,
string Constraint = "",
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
- (ins OpClass:$rs2, AVL:$vl, ixlenimm:$sew), []>,
+ (ins OpClass:$rs2, AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1049,8 +1061,8 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
string Constraint = "",
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$rm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ (ins RetClass:$passthru, OpClass:$rs2, vec_rm:$rm,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1070,7 +1082,7 @@ class VPseudoUnaryMask<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1089,8 +1101,8 @@ class VPseudoUnaryMaskRoundingMode<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
- VMaskOp:$vm, ixlenimm:$rm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, vec_rm:$rm,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1110,7 +1122,7 @@ class VPseudoUnaryMask_NoExcept<VReg RetClass,
string Constraint = ""> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> {
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1127,8 +1139,8 @@ class VPseudoUnaryNoMask_FRM<VReg RetClass,
string Constraint = "",
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$frm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ (ins RetClass:$passthru, OpClass:$rs2, vec_rm:$frm,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1147,8 +1159,8 @@ class VPseudoUnaryMask_FRM<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
- VMaskOp:$vm, ixlenimm:$frm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, vec_rm:$frm,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1164,7 +1176,7 @@ class VPseudoUnaryMask_FRM<VReg RetClass,
class VPseudoUnaryNoMaskGPROut :
Pseudo<(outs GPR:$rd),
- (ins VR:$rs2, AVL:$vl, ixlenimm:$sew), []>,
+ (ins VR:$rs2, AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1175,7 +1187,7 @@ class VPseudoUnaryNoMaskGPROut :
class VPseudoUnaryMaskGPROut :
Pseudo<(outs GPR:$rd),
- (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
+ (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1189,7 +1201,7 @@ class VPseudoUnaryAnyMask<VReg RetClass,
VReg Op1Class> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, Op1Class:$rs2,
- VR:$vm, AVL:$vl, ixlenimm:$sew), []>,
+ VR:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1205,7 +1217,7 @@ class VPseudoBinaryNoMask<VReg RetClass,
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
- (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
+ (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1223,7 +1235,7 @@ class VPseudoBinaryNoMaskPolicy<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl,
- ixlenimm:$sew, ixlenimm:$policy), []>,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1242,8 +1254,8 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
int UsesVXRM_ = 1,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, vec_rm:$rm,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1265,8 +1277,8 @@ class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, ixlenimm:$rm, AVL:$vl,
- ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, vec_rm:$rm, AVL:$vl,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1288,8 +1300,8 @@ class VPseudoTiedBinaryNoMask<VReg RetClass,
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew,
- ixlenimm:$policy), []>,
+ (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew,
+ vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1309,9 +1321,9 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs2, Op2Class:$rs1,
- ixlenimm:$rm,
- AVL:$vl, ixlenimm:$sew,
- ixlenimm:$policy), []>,
+ vec_rm:$rm,
+ AVL:$vl, sew:$sew,
+ vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1331,7 +1343,7 @@ class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered>:
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
- ixlenimm:$sew),[]>,
+ sew:$sew),[]>,
RISCVVPseudo,
RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 0;
@@ -1345,7 +1357,7 @@ class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered>:
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew),[]>,
RISCVVPseudo,
RISCVVSX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 0;
@@ -1363,7 +1375,7 @@ class VPseudoBinaryMaskPolicy<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1382,7 +1394,7 @@ class VPseudoTernaryMaskPolicy<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1400,8 +1412,8 @@ class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm,
- ixlenimm:$rm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ vec_rm:$rm,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1423,7 +1435,7 @@ class VPseudoBinaryMOutMask<VReg RetClass,
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1445,7 +1457,7 @@ class VPseudoTiedBinaryMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1467,8 +1479,8 @@ class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op2Class:$rs1,
VMaskOp:$vm,
- ixlenimm:$rm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ vec_rm:$rm,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
...
[truncated]
|
wangpc-pp
approved these changes
Oct 30, 2024
lenary
approved these changes
Oct 30, 2024
preames
approved these changes
Oct 30, 2024
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preames
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preames
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LGTM, but it feels a bit weird to have a single operand type for both VXRM and FRM. Do we have a single instruction/pseudo which dynamically could be either? If not, why not split the operand type by FRM and VXRM?
Collaborator
Author
The tablegen bases classes are shared and take an argument for UsesVXRM. I could use that to select different operand types in the |
mshockwave
reviewed
Oct 30, 2024
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mshockwave
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Are we gonna use these new OperandTypes instead of TSFlags to retrieve the operand index of SEW, VecPolicy etc.?
Collaborator
Author
I hadn't planned on it. Seems more expensive to scan the operand types to find the operands. I might use them to drop the operands in RISCVAsmPrinter. |
Member
It gives us more flexibility in a long run because we no longer need to (semi-)hardcode operand offset of these operands. But I agree at this moment it's easier to keep the current way, at least for |
Collaborator
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smallp-o-p
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Nov 3, 2024
Use TSFlags to distinquish which type of rounding mode it is. We use the same tablegen base classes for vxrm and frm sometimes so its hard to have different types for different instructions.
NoumanAmir657
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Nov 4, 2024
Use TSFlags to distinquish which type of rounding mode it is. We use the same tablegen base classes for vxrm and frm sometimes so its hard to have different types for different instructions.
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Use TSFlags to distinquish which type of rounding mode it is.
Stacked on #114168