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[RISCV] Add OperandType for vector rounding mode operands. #114179

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Merged
merged 5 commits into from
Oct 30, 2024
Merged

[RISCV] Add OperandType for vector rounding mode operands. #114179

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b5303f6
[RISCV] Add OperandType for sew and vecpolicy operands.
topperc Oct 30, 2024
dcbb655
fixup! rename vecpolicy -> vec_policy.
topperc Oct 30, 2024
9948a6e
Merge remote-tracking branch 'origin/main' into pr/sew-vecpolicy
topperc Oct 30, 2024
fba5145
[RISCV] Add OperandType for vector rounding mode operands.
topperc Oct 30, 2024
bacf0f2
Merge remote-tracking branch 'origin/main' into pr/rounding-mode
topperc Oct 30, 2024
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4 changes: 3 additions & 1 deletion llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -341,7 +341,9 @@ enum OperandType : unsigned {
OPERAND_VEC_POLICY,
// Vector SEW operand.
OPERAND_SEW,
OPERAND_LAST_RISCV_IMM = OPERAND_SEW,
// Vector rounding mode for VXRM or FRM.
OPERAND_VEC_RM,
OPERAND_LAST_RISCV_IMM = OPERAND_VEC_RM,
// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli
// or vsetivli.
Expand Down
7 changes: 7 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Expand Up @@ -2551,6 +2551,13 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_SEW:
Ok = Imm == 0 || (Imm >= 3 && Imm <= 6);
break;
case RISCVOp::OPERAND_VEC_RM:
assert(RISCVII::hasRoundModeOp(Desc.TSFlags));
if (RISCVII::usesVXRM(Desc.TSFlags))
Ok = isUInt<2>(Imm);
else
Ok = RISCVFPRndMode::isValidRoundingMode(Imm);
break;
}
if (!Ok) {
ErrInfo = "Invalid immediate";
Expand Down
24 changes: 14 additions & 10 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Expand Up @@ -92,6 +92,10 @@ def sew : RISCVOp {
let OperandType = "OPERAND_SEW";
}

def vec_rm : RISCVOp {
let OperandType = "OPERAND_VEC_RM";
}

// X0 has special meaning for vsetvl/vsetvli.
// rd | rs1 | AVL value | Effect on vl
//--------------------------------------------------------------
Expand Down Expand Up @@ -1057,7 +1061,7 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
string Constraint = "",
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$rm,
(ins RetClass:$passthru, OpClass:$rs2, vec_rm:$rm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
Expand Down Expand Up @@ -1097,7 +1101,7 @@ class VPseudoUnaryMaskRoundingMode<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
VMaskOp:$vm, ixlenimm:$rm,
VMaskOp:$vm, vec_rm:$rm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
Expand Down Expand Up @@ -1135,7 +1139,7 @@ class VPseudoUnaryNoMask_FRM<VReg RetClass,
string Constraint = "",
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$frm,
(ins RetClass:$passthru, OpClass:$rs2, vec_rm:$frm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
Expand All @@ -1155,7 +1159,7 @@ class VPseudoUnaryMask_FRM<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
VMaskOp:$vm, ixlenimm:$frm,
VMaskOp:$vm, vec_rm:$frm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
Expand Down Expand Up @@ -1250,7 +1254,7 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
int UsesVXRM_ = 1,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm,
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, vec_rm:$rm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
Expand All @@ -1273,7 +1277,7 @@ class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm, ixlenimm:$rm, AVL:$vl,
VMaskOp:$vm, vec_rm:$rm, AVL:$vl,
sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
Expand Down Expand Up @@ -1317,7 +1321,7 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs2, Op2Class:$rs1,
ixlenimm:$rm,
vec_rm:$rm,
AVL:$vl, sew:$sew,
vec_policy:$policy), []>,
RISCVVPseudo {
Expand Down Expand Up @@ -1408,7 +1412,7 @@ class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm,
ixlenimm:$rm,
vec_rm:$rm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
Expand Down Expand Up @@ -1475,7 +1479,7 @@ class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op2Class:$rs1,
VMaskOp:$vm,
ixlenimm:$rm,
vec_rm:$rm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
Expand Down Expand Up @@ -1578,7 +1582,7 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
ixlenimm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
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Expand Up @@ -559,7 +559,7 @@ define <vscale x 1 x float> @after_fsrm3(<vscale x 1 x float> %0, <vscale x 1 x
; CHECK-LABEL: after_fsrm3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi 4
; CHECK-NEXT: fsrmi a1, 5
; CHECK-NEXT: fsrmi a1, 3
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: fsrm a1
Expand All @@ -568,7 +568,7 @@ define <vscale x 1 x float> @after_fsrm3(<vscale x 1 x float> %0, <vscale x 1 x
; UNOPT-LABEL: after_fsrm3:
; UNOPT: # %bb.0: # %entry
; UNOPT-NEXT: fsrmi 4
; UNOPT-NEXT: fsrmi a1, 5
; UNOPT-NEXT: fsrmi a1, 3
; UNOPT-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; UNOPT-NEXT: vfadd.vv v8, v8, v9
; UNOPT-NEXT: fsrm a1
Expand All @@ -579,7 +579,7 @@ entry:
<vscale x 1 x float> undef,
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
i64 5, i64 %2)
i64 3, i64 %2)
ret <vscale x 1 x float> %a
}

Expand Down
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