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[RISCV][GISel] Add fcopysign tests with mismatched types. NFC #115364

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Merged
merged 1 commit into from
Nov 8, 2024
Merged

[RISCV][GISel] Add fcopysign tests with mismatched types. NFC #115364

merged 1 commit into from
Nov 8, 2024

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@topperc
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@topperc topperc commented Nov 7, 2024

fcopysign takes two operands, one for the magnitude and exponent and the other for the sign. The result type is determined by the magnitude and exponent operand. The sign operand does not need to be the same type. Note, in IR all 3 types must match.

We have isel patterns for all possible combinations of types and the legalizer thinks they are all legal, but we had no tests for it. I was unable to find any combiner rules that would create an instruction with mismatch types.

@topperc
[RISCV][GISel] Add fcopysign tests with mismatched types.
547f3fb 
fcopysign takes two operands, one for the magnitude and exponent
and the other for the sign. The result type is determined by the
magnitude and exponent operand. The sign operand does not need to
be the same type. Note, in IR all 3 types must match.

We have isel patterns for all possible combinations of types and
the legalizer thinks they are all legal, but we had no tests for it.
I was unable to find any combiner rules that would create an
instruction with mismatch types.
@topperc topperc changed the title [RISCV][GISel] Add fcopysign tests with mismatched types. [RISCV][GISel] Add fcopysign tests with mismatched types. NFC Nov 7, 2024
@llvmbot
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llvmbot commented Nov 7, 2024

@llvm/pr-subscribers-llvm-globalisel

Author: Craig Topper (topperc)

Changes

fcopysign takes two operands, one for the magnitude and exponent and the other for the sign. The result type is determined by the magnitude and exponent operand. The sign operand does not need to be the same type. Note, in IR all 3 types must match.

We have isel patterns for all possible combinations of types and the legalizer thinks they are all legal, but we had no tests for it. I was unable to find any combiner rules that would create an instruction with mismatch types.

Patch is 21.09 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/115364.diff

6 Files Affected:

  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir (+104-4)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir (+54-4)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir (+88-4)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir (+46-4)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir (+96-4)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir (+50-4)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir
index 96f019948537fd..855764a8b8c09e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
+# RUN: llc -mtriple=riscv32 -mattr=+zfh,+d -run-pass=instruction-select \
 # RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
+# RUN: llc -mtriple=riscv64 -mattr=+zfh,+d -run-pass=instruction-select \
 # RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
 
 ---
@@ -241,7 +241,7 @@ body:             |
 
 ...
 ---
-name:            fcopysign_f16
+name:            fcopysign_f16_f16
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -249,7 +249,7 @@ body:             |
   bb.0:
     liveins: $f10_h, $f11_h
 
-    ; CHECK-LABEL: name: fcopysign_f16
+    ; CHECK-LABEL: name: fcopysign_f16_f16
     ; CHECK: liveins: $f10_h, $f11_h
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
@@ -264,3 +264,103 @@ body:             |
     PseudoRET implicit $f10_h
 
 ...
+---
+name:            fcopysign_f16_f32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f10_h, $f11_f
+
+    ; CHECK-LABEL: name: fcopysign_f16_f32
+    ; CHECK: liveins: $f10_h, $f11_f
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
+    ; CHECK-NEXT: [[FCVT_H_S:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_S [[COPY1]], 7
+    ; CHECK-NEXT: [[FSGNJ_H:%[0-9]+]]:fpr16 = FSGNJ_H [[COPY]], [[FCVT_H_S]]
+    ; CHECK-NEXT: $f10_h = COPY [[FSGNJ_H]]
+    ; CHECK-NEXT: PseudoRET implicit $f10_h
+    %0:fprb(s16) = COPY $f10_h
+    %1:fprb(s32) = COPY $f11_f
+    %2:fprb(s16) = G_FCOPYSIGN %0, %1
+    $f10_h = COPY %2(s16)
+    PseudoRET implicit $f10_h
+
+...
+---
+name:            fcopysign_f32_f16
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f10_f, $f11_h
+
+    ; CHECK-LABEL: name: fcopysign_f32_f16
+    ; CHECK: liveins: $f10_f, $f11_h
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+    ; CHECK-NEXT: [[FCVT_S_H:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_H [[COPY1]], 0
+    ; CHECK-NEXT: [[FSGNJ_S:%[0-9]+]]:fpr32 = FSGNJ_S [[COPY]], [[FCVT_S_H]]
+    ; CHECK-NEXT: $f10_f = COPY [[FSGNJ_S]]
+    ; CHECK-NEXT: PseudoRET implicit $f10_f
+    %0:fprb(s32) = COPY $f10_f
+    %1:fprb(s16) = COPY $f11_h
+    %2:fprb(s32) = G_FCOPYSIGN %0, %1
+    $f10_f = COPY %2(s32)
+    PseudoRET implicit $f10_f
+
+...
+---
+name:            fcopysign_f16_f64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f10_h, $f11_d
+
+    ; CHECK-LABEL: name: fcopysign_f16_f64
+    ; CHECK: liveins: $f10_h, $f11_d
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
+    ; CHECK-NEXT: [[FCVT_H_D:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_D [[COPY1]], 7
+    ; CHECK-NEXT: [[FSGNJ_H:%[0-9]+]]:fpr16 = FSGNJ_H [[COPY]], [[FCVT_H_D]]
+    ; CHECK-NEXT: $f10_h = COPY [[FSGNJ_H]]
+    ; CHECK-NEXT: PseudoRET implicit $f10_h
+    %0:fprb(s16) = COPY $f10_h
+    %1:fprb(s64) = COPY $f11_d
+    %2:fprb(s16) = G_FCOPYSIGN %0, %1
+    $f10_h = COPY %2(s16)
+    PseudoRET implicit $f10_h
+
+...
+---
+name:            fcopysign_f64_f16
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f10_d, $f11_h
+
+    ; CHECK-LABEL: name: fcopysign_f64_f16
+    ; CHECK: liveins: $f10_d, $f11_h
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+    ; CHECK-NEXT: [[FCVT_D_H:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_H [[COPY1]], 0
+    ; CHECK-NEXT: [[FSGNJ_D:%[0-9]+]]:fpr64 = FSGNJ_D [[COPY]], [[FCVT_D_H]]
+    ; CHECK-NEXT: $f10_d = COPY [[FSGNJ_D]]
+    ; CHECK-NEXT: PseudoRET implicit $f10_d
+    %0:fprb(s64) = COPY $f10_d
+    %1:fprb(s16) = COPY $f11_h
+    %2:fprb(s64) = G_FCOPYSIGN %0, %1
+    $f10_d = COPY %2(s64)
+    PseudoRET implicit $f10_d
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
index 037647ae688725..45cba58875341e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
@@ -241,7 +241,7 @@ body:             |
 
 ...
 ---
-name:            fcopysign_f32
+name:            fcopysign_f32_f32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -249,7 +249,7 @@ body:             |
   bb.0:
     liveins: $f10_f, $f11_f
 
-    ; CHECK-LABEL: name: fcopysign_f32
+    ; CHECK-LABEL: name: fcopysign_f32_f32
     ; CHECK: liveins: $f10_f, $f11_f
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
@@ -263,6 +263,31 @@ body:             |
     $f10_f = COPY %2(s32)
     PseudoRET implicit $f10_f
 
+...
+---
+name:            fcopysign_f32_f64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f10_f, $f11_d
+
+    ; CHECK-LABEL: name: fcopysign_f32_f64
+    ; CHECK: liveins: $f10_f, $f11_d
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
+    ; CHECK-NEXT: [[FCVT_S_D:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_D [[COPY1]], 7
+    ; CHECK-NEXT: [[FSGNJ_S:%[0-9]+]]:fpr32 = FSGNJ_S [[COPY]], [[FCVT_S_D]]
+    ; CHECK-NEXT: $f10_f = COPY [[FSGNJ_S]]
+    ; CHECK-NEXT: PseudoRET implicit $f10_f
+    %0:fprb(s32) = COPY $f10_f
+    %1:fprb(s64) = COPY $f11_d
+    %2:fprb(s32) = G_FCOPYSIGN %0, %1
+    $f10_f = COPY %2(s32)
+    PseudoRET implicit $f10_f
+
 ...
 ---
 name:            fadd_f64
@@ -501,7 +526,7 @@ body:             |
 
 ...
 ---
-name:            fcopysign_f64
+name:            fcopysign_f64_f64
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
@@ -509,7 +534,7 @@ body:             |
   bb.0:
     liveins: $f10_d, $f11_d
 
-    ; CHECK-LABEL: name: fcopysign_f64
+    ; CHECK-LABEL: name: fcopysign_f64_f64
     ; CHECK: liveins: $f10_d, $f11_d
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
@@ -524,3 +549,28 @@ body:             |
     PseudoRET implicit $f10_d
 
 ...
+---
+name:            fcopysign_f64_f32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f10_d, $f11_f
+
+    ; CHECK-LABEL: name: fcopysign_f64_f32
+    ; CHECK: liveins: $f10_d, $f11_f
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
+    ; CHECK-NEXT: [[FCVT_D_S:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_S [[COPY1]], 0
+    ; CHECK-NEXT: [[FSGNJ_D:%[0-9]+]]:fpr64 = FSGNJ_D [[COPY]], [[FCVT_D_S]]
+    ; CHECK-NEXT: $f10_d = COPY [[FSGNJ_D]]
+    ; CHECK-NEXT: PseudoRET implicit $f10_d
+    %0:fprb(s64) = COPY $f10_d
+    %1:fprb(s32) = COPY $f11_f
+    %2:fprb(s64) = G_FCOPYSIGN %0, %1
+    $f10_d = COPY %2(s64)
+    PseudoRET implicit $f10_d
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir
index f1777e945b12db..f9e459271e640d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=legalizer %s -o - \
+# RUN: llc -mtriple=riscv32 -mattr=+zfh,+d -run-pass=legalizer %s -o - \
 # RUN: | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=legalizer %s -o - \
+# RUN: llc -mtriple=riscv64 -mattr=+zfh,+d -run-pass=legalizer %s -o - \
 # RUN: | FileCheck %s
 
 ---
@@ -211,12 +211,12 @@ body:             |
 
 ...
 ---
-name:            fcopysign_f16
+name:            fcopysign_f16_f16
 body:             |
   bb.0:
     liveins: $f10_h, $f11_h
 
-    ; CHECK-LABEL: name: fcopysign_f16
+    ; CHECK-LABEL: name: fcopysign_f16_f16
     ; CHECK: liveins: $f10_h, $f11_h
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
@@ -231,3 +231,87 @@ body:             |
     PseudoRET implicit $f10_h
 
 ...
+---
+name:            fcopysign_f16_f32
+body:             |
+  bb.0:
+    liveins: $f10_h, $f11_f
+
+    ; CHECK-LABEL: name: fcopysign_f16_f32
+    ; CHECK: liveins: $f10_h, $f11_f
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+    ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s32)
+    ; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16)
+    ; CHECK-NEXT: PseudoRET implicit $f10_h
+    %0:_(s16) = COPY $f10_h
+    %1:_(s32) = COPY $f11_f
+    %2:_(s16) = G_FCOPYSIGN %0, %1
+    $f10_h = COPY %2(s16)
+    PseudoRET implicit $f10_h
+
+...
+---
+name:            fcopysign_f32_f16
+body:             |
+  bb.0:
+    liveins: $f10_f, $f11_h
+
+    ; CHECK-LABEL: name: fcopysign_f32_f16
+    ; CHECK: liveins: $f10_f, $f11_h
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
+    ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s32) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16)
+    ; CHECK-NEXT: $f10_f = COPY [[FCOPYSIGN]](s32)
+    ; CHECK-NEXT: PseudoRET implicit $f10_f
+    %0:_(s32) = COPY $f10_f
+    %1:_(s16) = COPY $f11_h
+    %2:_(s32) = G_FCOPYSIGN %0, %1
+    $f10_f = COPY %2(s32)
+    PseudoRET implicit $f10_f
+
+...
+---
+name:            fcopysign_f16_f64
+body:             |
+  bb.0:
+    liveins: $f10_h, $f11_d
+
+    ; CHECK-LABEL: name: fcopysign_f16_f64
+    ; CHECK: liveins: $f10_h, $f11_d
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d
+    ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s64)
+    ; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16)
+    ; CHECK-NEXT: PseudoRET implicit $f10_h
+    %0:_(s16) = COPY $f10_h
+    %1:_(s64) = COPY $f11_d
+    %2:_(s16) = G_FCOPYSIGN %0, %1
+    $f10_h = COPY %2(s16)
+    PseudoRET implicit $f10_h
+
+...
+---
+name:            fcopysign_f64_f16
+body:             |
+  bb.0:
+    liveins: $f10_d, $f11_h
+
+    ; CHECK-LABEL: name: fcopysign_f64_f16
+    ; CHECK: liveins: $f10_d, $f11_h
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
+    ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s64) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16)
+    ; CHECK-NEXT: $f10_d = COPY [[FCOPYSIGN]](s64)
+    ; CHECK-NEXT: PseudoRET implicit $f10_d
+    %0:_(s64) = COPY $f10_d
+    %1:_(s16) = COPY $f11_h
+    %2:_(s64) = G_FCOPYSIGN %0, %1
+    $f10_d = COPY %2(s64)
+    PseudoRET implicit $f10_d
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir
index 599779d09c2c15..af4feac4e62fe3 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir
@@ -211,12 +211,12 @@ body:             |
 
 ...
 ---
-name:            fcopysign_f32
+name:            fcopysign_f32_f32
 body:             |
   bb.0:
     liveins: $f10_f, $f11_f
 
-    ; CHECK-LABEL: name: fcopysign_f32
+    ; CHECK-LABEL: name: fcopysign_f32_f32
     ; CHECK: liveins: $f10_f, $f11_f
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
@@ -230,6 +230,27 @@ body:             |
     $f10_f = COPY %2(s32)
     PseudoRET implicit $f10_f
 
+...
+---
+name:            fcopysign_f32_f64
+body:             |
+  bb.0:
+    liveins: $f10_f, $f11_d
+
+    ; CHECK-LABEL: name: fcopysign_f32_f64
+    ; CHECK: liveins: $f10_f, $f11_d
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d
+    ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s32) = G_FCOPYSIGN [[COPY]], [[COPY1]](s64)
+    ; CHECK-NEXT: $f10_f = COPY [[FCOPYSIGN]](s32)
+    ; CHECK-NEXT: PseudoRET implicit $f10_f
+    %0:_(s32) = COPY $f10_f
+    %1:_(s64) = COPY $f11_d
+    %2:_(s32) = G_FCOPYSIGN %0, %1
+    $f10_f = COPY %2(s32)
+    PseudoRET implicit $f10_f
+
 ...
 ---
 name:            fadd_f64
@@ -438,12 +459,12 @@ body:             |
 
 ...
 ---
-name:            fcopysign_f64
+name:            fcopysign_f64_f64
 body:             |
   bb.0:
     liveins: $f10_d, $f11_d
 
-    ; CHECK-LABEL: name: fcopysign_f64
+    ; CHECK-LABEL: name: fcopysign_f64_f64
     ; CHECK: liveins: $f10_d, $f11_d
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
@@ -458,3 +479,24 @@ body:             |
     PseudoRET implicit $f10_d
 
 ...
+---
+name:            fcopysign_f64_f32
+body:             |
+  bb.0:
+    liveins: $f10_d, $f11_f
+
+    ; CHECK-LABEL: name: fcopysign_f64_f32
+    ; CHECK: liveins: $f10_d, $f11_f
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+    ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s64) = G_FCOPYSIGN [[COPY]], [[COPY1]](s32)
+    ; CHECK-NEXT: $f10_d = COPY [[FCOPYSIGN]](s64)
+    ; CHECK-NEXT: PseudoRET implicit $f10_d
+    %0:_(s64) = COPY $f10_d
+    %1:_(s32) = COPY $f11_f
+    %2:_(s64) = G_FCOPYSIGN %0, %1
+    $f10_d = COPY %2(s64)
+    PseudoRET implicit $f10_d
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
index ace4aa542377b3..1ef5c48f0b5b67 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
@@ -1,8 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+zfh,+d -run-pass=regbankselect \
 # RUN:   -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+zfh,+d -run-pass=regbankselect \
 # RUN:   -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck %s
 
@@ -233,14 +233,14 @@ body:             |
 
 ...
 ---
-name:            fcopysign_f16
+name:            fcopysign_f16_f16
 legalized:       true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $f10_h, $f11_h
 
-    ; CHECK-LABEL: name: fcopysign_f16
+    ; CHECK-LABEL: name: fcopysign_f16_f16
     ; CHECK: liveins: $f10_h, $f11_h
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
@@ -255,3 +255,95 @@ body:             |
     PseudoRET implicit $f10_h
 
 ...
+---
+name:            fcopysign_f16_f32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f10_h, $f11_f
+
+    ; CHECK-LABEL: name: fcopysign_f16_f32
+    ; CHECK: liveins: $f10_h, $f11_f
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f
+    ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s32)
+    ; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16)
+    ; CHECK-NEXT: PseudoRET implicit $f10_h
+    %0:_(s16) = COPY $f10_h
+    %1:_(s32) = COPY $f11_f
+    %2:_(s16) = G_FCOPYSIGN %0, %1
+    $f10_h = COPY %2(s16)
+    PseudoRET implicit $f10_h
+
+...
+---
+name:            fcopysign_f32_f16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f10_f, $f11_h
+
+    ; CHECK-LABEL: name: fcopysign_f32_f16
+    ; CHECK: liveins: $f10_f, $f11_h
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
+    ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s32) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16)
+    ; CHECK-NEXT: $f10_f = COPY [[FCOPYSIGN]](s32)
+    ; CHECK-NEXT: PseudoRET implicit $f10_f
+    %0:_(s32) = COPY $f10_f
+    %1:_(s16) = COPY $f11_h
+    %2:_(s32) = G_FCOPYSIGN %0, %1
+    $f10_f = COPY %2(s32)
+    PseudoRET implicit $f10_f
+
+...
+---
+name:            fcopysign_f16_f64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f10_h, $f11_d
+
+    ; CHECK-LABEL: name: fcopysign_f16_f64
+    ; CHECK: liveins: $f10_h, $f11_d
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d
+    ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s64)
+    ; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16)
+    ; CHECK-NEXT: PseudoRET implicit $f10_h
+    %0:_(s16) = COPY $f10_h
+    %1:_(s64) = COPY $f11_d
+    %2:_(s16) = G_FCOPYSIGN %0, %1
+    $f10_h = COPY %2(s16)
+    PseudoRET implicit $f10_h
+
+...
+---
+name:            fcopysign_f64_f16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f10_d, $f11_h
+
+    ; CHECK-LABEL: name: fcopysign_f64_f16
+    ; CHECK: liveins: $f10_d, $f11_h
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
+    ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s64) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16)
+    ; CHECK-NEXT: $f10_d = COPY [[FCOPYSIGN]](s64)
+    ; CHECK-NEXT: PseudoRET implicit $f10_d
+    %0:_(s64) = COPY $f10_d
+    %1:_(s16) = COPY $f11_h
+    %2:_(s64) = G_FCOPYSIGN %0, %1
+    $f10_d = COPY %2(s64)
+    PseudoRET implicit $f10_d
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
index 1ac6837a77bdb9..2801faf76820b2 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
@@ -233,14 +233,14 @@ body:             |
 
 ...
 ---
-name:            fcopysign_f32
+name:            fcopysign_f32_f32
 legalized:       true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $f10_f, $f11_f
 
-    ; CHECK-LABEL: name: fcopysign_f32
+    ; CHECK-LABEL: name: fcopysign_f32_f32
     ; CHECK: liveins: $f10_f, $f11_f
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
@@ -254,6 +254,29 @@ body:             |
     $f10_f = COPY %2(s32)
     PseudoRET implicit $f10_f
 
+...
+---
+name:            fcopysign_f32_f64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f10_f, $f11_d
+
+    ; CHECK-LABEL: name: fcopysign_f32_f64
+    ; CHECK: liveins: $f10_f, $f11_d
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d
+    ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s32) = G_FCOPYSIGN [[COPY]], [[COPY1]](s64)
+    ; CHECK-NEXT: $f10_f = COPY [[FCOPYSIGN]](s32)
+    ; CHECK-NEXT: PseudoRET implicit $f10_f
+    %0:_(s32) = COPY $f10_f
+    %1:_(s64) = COPY $f11_d
+    %2:_(s32) = G_FCOPYSIGN %0, %1
+    $f10_f = COPY %2(s32)
+    PseudoRET implicit $f10_f
+
 ...
 ---
 name:            fadd_f64
@@ -482,14 +505,14 @@ body:             |
 
 ...
 ---
-name:            fcopysign_f64
+name:            fcopysign_f64_f64
 legalized...
[truncated]

@topperc topperc merged commit 037f804 into llvm:main Nov 8, 2024
8 of 10 checks passed
@topperc topperc deleted the pr/fcopysign-tests branch November 8, 2024 01:07
Groverkss pushed a commit to iree-org/llvm-project that referenced this pull request Nov 15, 2024
@topperc @Groverkss
[RISCV][GISel] Add fcopysign tests with mismatched types. NFC (llvm#1…
c13369a 
…15364)

fcopysign takes two operands, one for the magnitude and exponent and the
other for the sign. The result type is determined by the magnitude and
exponent operand. The sign operand does not need to be the same type.
Note, in IR all 3 types must match.

We have isel patterns for all possible combinations of types and the
legalizer thinks they are all legal, but we had no tests for it. I was
unable to find any combiner rules that would create an instruction with
mismatch types.
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@arsenm arsenm arsenm approved these changes

@mshockwave mshockwave Awaiting requested review from mshockwave

@michaelmaitland michaelmaitland Awaiting requested review from michaelmaitland

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@topperc @llvmbot @arsenm