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[RISCV][GISel] Add fcopysign tests with mismatched types. NFC #115364

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Merged
merged 1 commit into from
Nov 8, 2024
Merged

[RISCV][GISel] Add fcopysign tests with mismatched types. NFC #115364

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108 changes: 104 additions & 4 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
# RUN: llc -mtriple=riscv32 -mattr=+zfh,+d -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
# RUN: llc -mtriple=riscv64 -mattr=+zfh,+d -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
Expand Down Expand Up @@ -241,15 +241,15 @@ body: |

...
---
name: fcopysign_f16
name: fcopysign_f16_f16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_h, $f11_h

; CHECK-LABEL: name: fcopysign_f16
; CHECK-LABEL: name: fcopysign_f16_f16
; CHECK: liveins: $f10_h, $f11_h
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
Expand All @@ -264,3 +264,103 @@ body: |
PseudoRET implicit $f10_h

...
---
name: fcopysign_f16_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_h, $f11_f

; CHECK-LABEL: name: fcopysign_f16_f32
; CHECK: liveins: $f10_h, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FCVT_H_S:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_S [[COPY1]], 7
; CHECK-NEXT: [[FSGNJ_H:%[0-9]+]]:fpr16 = FSGNJ_H [[COPY]], [[FCVT_H_S]]
; CHECK-NEXT: $f10_h = COPY [[FSGNJ_H]]
; CHECK-NEXT: PseudoRET implicit $f10_h
%0:fprb(s16) = COPY $f10_h
%1:fprb(s32) = COPY $f11_f
%2:fprb(s16) = G_FCOPYSIGN %0, %1
$f10_h = COPY %2(s16)
PseudoRET implicit $f10_h

...
---
name: fcopysign_f32_f16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_f, $f11_h

; CHECK-LABEL: name: fcopysign_f32_f16
; CHECK: liveins: $f10_f, $f11_h
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
; CHECK-NEXT: [[FCVT_S_H:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_H [[COPY1]], 0
; CHECK-NEXT: [[FSGNJ_S:%[0-9]+]]:fpr32 = FSGNJ_S [[COPY]], [[FCVT_S_H]]
; CHECK-NEXT: $f10_f = COPY [[FSGNJ_S]]
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:fprb(s32) = COPY $f10_f
%1:fprb(s16) = COPY $f11_h
%2:fprb(s32) = G_FCOPYSIGN %0, %1
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f

...
---
name: fcopysign_f16_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_h, $f11_d

; CHECK-LABEL: name: fcopysign_f16_f64
; CHECK: liveins: $f10_h, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FCVT_H_D:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_D [[COPY1]], 7
; CHECK-NEXT: [[FSGNJ_H:%[0-9]+]]:fpr16 = FSGNJ_H [[COPY]], [[FCVT_H_D]]
; CHECK-NEXT: $f10_h = COPY [[FSGNJ_H]]
; CHECK-NEXT: PseudoRET implicit $f10_h
%0:fprb(s16) = COPY $f10_h
%1:fprb(s64) = COPY $f11_d
%2:fprb(s16) = G_FCOPYSIGN %0, %1
$f10_h = COPY %2(s16)
PseudoRET implicit $f10_h

...
---
name: fcopysign_f64_f16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_d, $f11_h

; CHECK-LABEL: name: fcopysign_f64_f16
; CHECK: liveins: $f10_d, $f11_h
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
; CHECK-NEXT: [[FCVT_D_H:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_H [[COPY1]], 0
; CHECK-NEXT: [[FSGNJ_D:%[0-9]+]]:fpr64 = FSGNJ_D [[COPY]], [[FCVT_D_H]]
; CHECK-NEXT: $f10_d = COPY [[FSGNJ_D]]
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:fprb(s64) = COPY $f10_d
%1:fprb(s16) = COPY $f11_h
%2:fprb(s64) = G_FCOPYSIGN %0, %1
$f10_d = COPY %2(s64)
PseudoRET implicit $f10_d

...
58 changes: 54 additions & 4 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -241,15 +241,15 @@ body: |

...
---
name: fcopysign_f32
name: fcopysign_f32_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_f, $f11_f

; CHECK-LABEL: name: fcopysign_f32
; CHECK-LABEL: name: fcopysign_f32_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
Expand All @@ -263,6 +263,31 @@ body: |
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f

...
---
name: fcopysign_f32_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_f, $f11_d

; CHECK-LABEL: name: fcopysign_f32_f64
; CHECK: liveins: $f10_f, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FCVT_S_D:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_D [[COPY1]], 7
; CHECK-NEXT: [[FSGNJ_S:%[0-9]+]]:fpr32 = FSGNJ_S [[COPY]], [[FCVT_S_D]]
; CHECK-NEXT: $f10_f = COPY [[FSGNJ_S]]
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:fprb(s32) = COPY $f10_f
%1:fprb(s64) = COPY $f11_d
%2:fprb(s32) = G_FCOPYSIGN %0, %1
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f

...
---
name: fadd_f64
Expand Down Expand Up @@ -501,15 +526,15 @@ body: |

...
---
name: fcopysign_f64
name: fcopysign_f64_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_d, $f11_d

; CHECK-LABEL: name: fcopysign_f64
; CHECK-LABEL: name: fcopysign_f64_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
Expand All @@ -524,3 +549,28 @@ body: |
PseudoRET implicit $f10_d

...
---
name: fcopysign_f64_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_d, $f11_f

; CHECK-LABEL: name: fcopysign_f64_f32
; CHECK: liveins: $f10_d, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FCVT_D_S:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_S [[COPY1]], 0
; CHECK-NEXT: [[FSGNJ_D:%[0-9]+]]:fpr64 = FSGNJ_D [[COPY]], [[FCVT_D_S]]
; CHECK-NEXT: $f10_d = COPY [[FSGNJ_D]]
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:fprb(s64) = COPY $f10_d
%1:fprb(s32) = COPY $f11_f
%2:fprb(s64) = G_FCOPYSIGN %0, %1
$f10_d = COPY %2(s64)
PseudoRET implicit $f10_d

...
92 changes: 88 additions & 4 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir
View file
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=legalizer %s -o - \
# RUN: llc -mtriple=riscv32 -mattr=+zfh,+d -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=legalizer %s -o - \
# RUN: llc -mtriple=riscv64 -mattr=+zfh,+d -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s

---
Expand Down Expand Up @@ -211,12 +211,12 @@ body: |

...
---
name: fcopysign_f16
name: fcopysign_f16_f16
body: |
bb.0:
liveins: $f10_h, $f11_h

; CHECK-LABEL: name: fcopysign_f16
; CHECK-LABEL: name: fcopysign_f16_f16
; CHECK: liveins: $f10_h, $f11_h
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
Expand All @@ -231,3 +231,87 @@ body: |
PseudoRET implicit $f10_h

...
---
name: fcopysign_f16_f32
body: |
bb.0:
liveins: $f10_h, $f11_f

; CHECK-LABEL: name: fcopysign_f16_f32
; CHECK: liveins: $f10_h, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s32)
; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16)
; CHECK-NEXT: PseudoRET implicit $f10_h
%0:_(s16) = COPY $f10_h
%1:_(s32) = COPY $f11_f
%2:_(s16) = G_FCOPYSIGN %0, %1
$f10_h = COPY %2(s16)
PseudoRET implicit $f10_h

...
---
name: fcopysign_f32_f16
body: |
bb.0:
liveins: $f10_f, $f11_h

; CHECK-LABEL: name: fcopysign_f32_f16
; CHECK: liveins: $f10_f, $f11_h
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s32) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16)
; CHECK-NEXT: $f10_f = COPY [[FCOPYSIGN]](s32)
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:_(s32) = COPY $f10_f
%1:_(s16) = COPY $f11_h
%2:_(s32) = G_FCOPYSIGN %0, %1
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f

...
---
name: fcopysign_f16_f64
body: |
bb.0:
liveins: $f10_h, $f11_d

; CHECK-LABEL: name: fcopysign_f16_f64
; CHECK: liveins: $f10_h, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d
; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s64)
; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16)
; CHECK-NEXT: PseudoRET implicit $f10_h
%0:_(s16) = COPY $f10_h
%1:_(s64) = COPY $f11_d
%2:_(s16) = G_FCOPYSIGN %0, %1
$f10_h = COPY %2(s16)
PseudoRET implicit $f10_h

...
---
name: fcopysign_f64_f16
body: |
bb.0:
liveins: $f10_d, $f11_h

; CHECK-LABEL: name: fcopysign_f64_f16
; CHECK: liveins: $f10_d, $f11_h
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s64) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16)
; CHECK-NEXT: $f10_d = COPY [[FCOPYSIGN]](s64)
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:_(s64) = COPY $f10_d
%1:_(s16) = COPY $f11_h
%2:_(s64) = G_FCOPYSIGN %0, %1
$f10_d = COPY %2(s64)
PseudoRET implicit $f10_d

...
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